| Patent application number | Description | Published |
|---|
| 20080232487 | Synchronous spectrum sharing by dedicated networks using OFDM/OFDMA signaling - A system and method for synchronous spectrum sharing for a dedicated network in a wireless communication system based on orthogonal frequency-division multiplexing (OFDM) or orthogonal frequency division multiple access (OFDMA) signaling is disclosed. The system and method includes detecting a frame of a broadcast waveform and extracting idle spectrum information from a subframe associated with the dedicated subchannel to the secondary user node. The system allows transmitting data from the secondary user node in unused symbol slots identified in the idle spectrum information thereby making efficient use of unused or idle spectrum. Accordingly, secondary users of the wireless communication system can dynamically form ad-hoc mesh network communications in fixed or mobile scenarios. | 09-25-2008 |
| 20090144353 | Method and apparatus for efficient modulo multiplication - A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2 | 06-04-2009 |
| 20090319856 | Method and apparatus for software-defined radio LDPC decoder - A method and apparatus for decoding transmissions in a wireless communications network is provided. A receiver includes a receive path. The receive path includes a low density parity check (LDPC) decoder. The receiver is configured to receive encoded transmissions and perform low density parity check decoding operations using a CRISP decoder. The CRISP decoder includes a plurality of memory units, and a plurality of processors. | 12-24-2009 |
| 20090319857 | Method and apparatus for parallel processing multimode LDPC decoder - A method and apparatus for decoding transmissions in a wireless communications network is provided. A receiver includes a receive path. The receive path includes a decoder configured to perform low density parity check decoding. The decoder includes a number of Context Reconfigurable Instruction Set Processors (CRISPs). The CRISPs are configured to process received data in parallel. The decoder includes a plurality of memory units, and each of the CRISPs includes a plurality of processors. | 12-24-2009 |
| 20100146362 | Contention-free parallel processing multimode LDPC decoder - A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process. | 06-10-2010 |
| 20110047433 | SYSTEM AND METHOD FOR STRUCTURED LDPC CODE FAMILY WITH FIXED CODE LENGTH AND NO PUNCTURING - A family of low density parity check (LDPC) codes is generated based on a mother code having a highest code rate. The low density parity check (LDPC) codes include a codeword size of at least 1344. The LDPC codes also include a plurality of parity bits in a lower triangular form. The mother code is constructed by: selecting m number of rows and n number of columns; setting maximum column weights and row weights; designing a protograph matrix based on the set column weights and row weights and selected m and n; and selecting circulant blocks based on the protograph matrix. | 02-24-2011 |
| 20110066916 | SYSTEM AND METHOD FOR STRUCTURED LDPC CODE FAMILY - A low density parity check (LDPC) family of codes is constructed by: determining a protograph for a mother code for the LDPC family of codes. The protograph is lifted by a lifting factor to design code specific protograph for a code. The method also includes constructing a base matrix for the code. The base matrix is constructed by replacing each zero in the code specific protograph with a ‘−1’; and replacing each one in the code specific protograph with a corresponding value from the mother matrix. The LDPC code includes a codeword size of at least 1344, a plurality of information bits, and a plurality of parity bits. The LDPC code is based on a mother code of code length 672. | 03-17-2011 |
| 20110134969 | METHOD AND APPARATUS FOR PARALLEL PROCESSING TURBO DECODER - A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas configured to receive data; a plurality of memory units that store the received data; and a plurality of decoders configured to perform a Turbo decoding operation. Each of the plurality of decoders decodes at least a portion of the received data using at least a portion of a decoding matrix. The receiver also includes a data switch coupled between the plurality of decoders and the plurality of memory units. The data switch configured to vary a decode operation from an long term evolution (LTE) based operation to a Wideband Code Division Multiple Access (WCDMA) operation. | 06-09-2011 |
| 20110154155 | SYSTEM AND METHOD FOR CODING AND INTERLEAVING FOR SHORT FRAME SUPPORT IN VISIBLE LIGHT COMMUNICATION - A transmitter is capable of performing both Galois Field (GF) (16) and GF (256) encoding in a visual light communication system. The transmitter includes a GF (256) encoder. The transmitter also includes a first bit mapper configured to map a first number of bits to a second number of bits. The Galois Field (256) encoder is configured to receive and encode the second number of bits. The transmitter also includes a second bit mapper configured to map the second number of bits to the first number of bits. The transmitter also includes an interleaver unit that can pad bits based on a frame size and puncture the bits after interleaving and prior to transmission. | 06-23-2011 |
| 20110164881 | OPTICAL CLOCK RATE NEGOTIATION FOR SUPPORTING ASYMMETRIC CLOCK RATES FOR VISIBLE LIGHT COMMUNICATION - A method and apparatus conduct an optical clock rate negotiation to support asymmetric clock rates for visible light communication (VLC) in a VLC device. A first frame that includes a receiver clock rate supported by a first VLC device is transmitted at a predetermined clock rate. A response frame that includes a receiver clock rate supported by a second VLC device is received from the second VLC device. A transmission clock rate of the first VLC device is selected based on the response frame from the second VLC device. Subsequent frames for data communication are transmitted to the second VLC device at the selected transmission clock rate of the first device. Alternatively, when conducting optical clock negotiation in the PHY layer, multiple clock rates are supported within a single frame. | 07-07-2011 |
