Patent application number | Description | Published |
20090257265 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels. | 10-15-2009 |
20090258135 | Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing - A method of making a nonvolatile memory cell includes forming a steering element and forming a carbon resistivity switching material storage element by coating a carbon containing colloid. | 10-15-2009 |
20090258485 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 10-15-2009 |
20090258489 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode. | 10-15-2009 |
20100006811 | CARBON-BASED INTERFACE LAYER FOR A MEMORY DEVICE AND METHODS OF FORMING THE SAME - In a first aspect, a memory cell is provided that includes (1) a first conductor; (2) a reversible resistance-switching element formed above the first conductor including (a) a carbon-based resistivity switching material; and (b) a carbon-based interface layer coupled to the carbon-based resistivity switching material; (3) a steering element formed above the first conductor; and (4) a second conductor formed above the reversible resistance-switching element and the steering element. Numerous other aspects are provided. | 01-14-2010 |
20100006812 | CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME - Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided. | 01-14-2010 |
20100012914 | CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME - Methods of forming memory devices, and memory devices formed in accordance with such methods, are provided, the methods including forming a via above a first conductive layer, forming a nonconformal carbon-based resistivity-switchable material layer in the via and coupled to the first conductive layer; and forming a second conductive layer in the via, above and coupled to the nonconformal carbon-based resistivity-switchable material layer. Numerous other aspects are provided. | 01-21-2010 |
20100038620 | INTEGRATION METHODS FOR CARBON FILMS IN TWO- AND THREE-DIMENSIONAL MEMORIES AND MEMORIES FORMED THEREFROM - Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the pillar to form multiple memory cells. Memory cells formed from such methods, as well as numerous other aspects are also disclosed. | 02-18-2010 |
20100038623 | METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING - Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the memory element, but not the steering element, to form multiple memory cells that share a single steering element. Memory cells formed from such methods, as well as numerous other aspects are also disclosed. | 02-18-2010 |
20100078759 | MIIM DIODES HAVING STACKED STRUCTURE - A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises first and second electrode and first and second insulators arraigned as follows. An insulating region has a trench formed therein. The trench has a bottom and side walls. The first electrode, which comprises a first metal, is on the side walls and over the bottom of the trench. A first insulator has a first interface with the first electrode. At least a portion of the first insulator is within the trench. A second insulator has a second interface with the first insulator. At least a portion of the second insulator is within the trench. The second electrode, which comprises a second metal, is in contact with the second insulator. The second electrode at least partially fills the trench. | 04-01-2010 |
20100108982 | ELECTRONIC DEVICES INCLUDING CARBON NANO-TUBE FILMS HAVING CARBON-BASED LINERS, AND METHODS OF FORMING THE SAME - Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a carbon layer (“carbon liner”) above the CNT layer, wherein the carbon liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided. | 05-06-2010 |
20100124813 | Self-Aligned Three-Dimensional Non-Volatile Memory Fabrication - A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors. | 05-20-2010 |
20100163824 | MODULATION OF RESISTIVITY IN CARBON-BASED READ-WRITEABLE MATERIALS - In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (“MIM”) stack above a substrate, the MIM stack including a carbon-based switching material having a resistivity of at least 1×10 | 07-01-2010 |
20100167521 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 07-01-2010 |
20100176366 | Nonvolatile memory cell including carbon storage element formed on a silicide layer - A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars. | 07-15-2010 |
20110095257 | MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width. | 04-28-2011 |
20110095258 | MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME - Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first cross-sectional area, coupled to a reversible resistivity switching material, such as aC, having a region that has a second cross-sectional area smaller than the first cross-sectional area. | 04-28-2011 |
20110143538 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 06-16-2011 |
20110210306 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - A method of forming a reversible resistance-switching metal-carbon-metal (“MCM”) device is provided, the device including a first conducting layer, a second conducting layer, and a reversible resistance-switching element disposed between the first and second conducting layers, wherein the reversible resistance-switching element includes thermal CVD graphitic material and includes a highly resistive region that favors crack formation. Other aspects are also provided. | 09-01-2011 |
20110254126 | MEMORY CELL WITH CARBON SWITCHING MATERIAL HAVING A REDUCED CROSS-SECTIONAL AREA AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided. | 10-20-2011 |
20120193756 | DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME - In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided. | 08-02-2012 |
20120223414 | METHODS FOR INCREASING BOTTOM ELECTRODE PERFORMANCE IN CARBON-BASED MEMORY DEVICES - In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided. | 09-06-2012 |
20130237056 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 09-12-2013 |
20130313503 | METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING - A memory is described that includes a shared diode layer and a memory element coupled to the diode layer. The memory element has a pie slice-shape, and includes a sidewall having a carbon film thereon. Numerous other aspects are also disclosed. | 11-28-2013 |
20130320542 | Method of fabricating a self-aligned buried bit line for a vertical channel dram - A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less. | 12-05-2013 |
20130323920 | Method of fabricating a gate-all-around word line for a vertical channel dram - A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less. | 12-05-2013 |
20140004689 | Methods Of Doping Substrates With ALD | 01-02-2014 |
20140017403 | Methods For Depositing Oxygen Deficient Metal Films - Described are methods of depositing an oxygen deficient metal film by chemical reaction of at least one precursor having a predetermined oxygen deficiency on a substrate. An exemplary method includes, during a metal oxide deposition cycle, exposing the substrate to a metal reactant gas comprising a metal and an oxygen reactant gas comprising oxygen to form a layer containing a metal oxide on the substrate. During an oxygen deficient deposition cycle, exposing the substrate to a metal reactant gas comprising a metal and an additional reactant gas excluding oxygen to form a second layer at least one of a metal nitride and a mixed metal on the substrate during a second cycle, the second layer being oxygen deficient relative to the layer containing the metal oxide; and repeating the metal oxide deposition cycle and the oxygen deficient deposition cycle to form the oxygen deficient film having the predetermined oxygen deficiency. | 01-16-2014 |
20140273504 | SELECTIVE DEPOSITION BY LIGHT EXPOSURE - A substrate processing chamber comprising a chamber wall enclosing a process zone having an exhaust port, a substrate support to support a substrate in the process zone, a gas distributor for providing a deposition gas to the process zone, a solid state light source capable of irradiating substantially the entire surface of the substrate with light, and a gas energizer for energizing the deposition gas. | 09-18-2014 |