Patent application number | Description | Published |
20080249218 | Process for the manufacture of at least partially neutralized chlorosulfonated polyolefin elastomers in oil - An oil concentrate comprising oil and one or more at least partially neutralized chlorosulfonated polyolefin elastomers containing 0.5-50 weight percent chlorine and 0.25 to 5 weight percent sulfur is disclosed. | 10-09-2008 |
20080249243 | Partially neutralized chlorosulfonated polyolefin elastomers - Partially neutralized chlorosulfonated polyolefin elastomers containing 0.5-10 weight percent chlorine and 0.25 to 5 weight percent sulfur are prepared from polyolefin elastomer base resins selected from the group consisting of propylene/ethylene copolymers, ethylene/propylene/diene copolymers, isobutylene/diene copolymers, isobutylene homopolymers, hydrogenated styrene/butadiene block copolymers and hydrogenated styrene/isoprene block copolymers. | 10-09-2008 |
20080249253 | Partially neutralized chlorosulfonated polyolefin elastomers - At least partially neutralized chlorosulfonated ethylene/alpha-olefin elastomers containing 0.5-10 weight percent chlorine and 0.25 to 5 weight percent sulfur are prepared from ethylene/alpha-olefin copolymer base resins having a ratio of weight average molecular weight (Mw) to number average molecular weight (Mn) less than 3.5. | 10-09-2008 |
20080249254 | Process for chlorosulfonating polyolefins - Chlorosulfonated polyolefin elastomers containing 0.5-10 weight percent chlorine and 0.25 to 5 weight percent sulfur are prepared in a low temperature (50° to 75° C.) solution process employing a chlorosulfonation agent of sulfuryl chloride or the combination of Cl | 10-09-2008 |
Patent application number | Description | Published |
20120146658 | DEBUG STATE MACHINE CROSS TRIGGERING - An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal. | 06-14-2012 |
20120150474 | DEBUG STATE MACHINE CROSS TRIGGERING - In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred. | 06-14-2012 |
Patent application number | Description | Published |
20100211336 | DATA PROCESSING INTERFACE DEVICE - Information of a first type is determined at an integrated circuit die of a data processing device included an integrated circuit package. The integrated circuit package includes the first integrated circuit die and a second integrated circuit die. Information of a second type is determined at the integrated circuit die. The first and second type of information is transmitted from the integrated circuit die to another integrated circuit die using a time-divided multiplexed protocol by transmitting the first information during a first time slot of the protocol and transmitting the second information during a second time slot of the protocol. | 08-19-2010 |
20110024800 | Shared Resources in a Chip Multiprocessor - In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor). | 02-03-2011 |
20120096288 | CONTROLLING OPERATION OF TEMPERATURE SENSORS - Techniques are disclosed relating to controlling power consumption of temperature sensors in integrated circuits. In one embodiment, an integrated circuit is disclosed that includes a temperature sensor that is configured to determine a temperature of the integrated circuit. The integrated circuit also includes a sensor controller that is configured to vary power consumption of the temperature sensor based, at least in part, on the determined temperature. In some embodiments, the integrated circuit may determine a sampling rate of the temperature sensor based, at least in part, on the determined temperature and a temperature threshold of the integrated circuit. The integrated circuit may then vary the power consumption of the temperature sensor by periodically disabling the temperature sensor based on the determined sampling rate. In some embodiments, the integrated circuit may also vary the power consumption of the temperature sensor based on the operating state of one or more processing cores in the integrated circuit. | 04-19-2012 |