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Enicks
Darwin Enicks, Colorado Springs, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20090189159 | GETTERING LAYER ON SUBSTRATE - Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region. | 07-30-2009 |
| 20100018554 | EX-SITU COMPONENT RECOVERY - Disclosed herein are devices, methods and systems for ex-situ component recovery. The ex-situ recovery can be performed by desorbing or outgassing components of a processing system in a recovery system, rather than in the processing system itself. The recovery system can include a docking station and/or a heated vacuum chamber. The heated vacuum chamber can be used to desorb or outgas components that will be located inside the processing system, while the docking station can be used to desorb or outgas components that will be connected to the processing system. The processing system components can be placed under pressure by the recovery system to desorb or outgas contaminants and remove virtual leaks. The recovery system pressure can include a vacuum roughing pump, a turbomolecular pump, and/or a cryogenic pump to apply a pressure necessary to desorb or outgas the components. | 01-28-2010 |
Darwin G. Enicks, Painted Post, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110073907 | INTEGRATED CIRCUIT STRUCTURES CONTAINING A STRAIN-COMPENSATED COMPOUND SEMICONDUCTOR LAYER AND METHODS AND SYSTEMS RELATED THERETO - A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein. | 03-31-2011 |
Darwin G. Enicks, Colorado Springs, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20080237716 | INTEGRATED CIRCUIT STRUCTURES HAVING A BORON ETCH-STOP LAYER AND METHODS, DEVICES AND SYSTEMS RELATED THERETO - An integrated circuit structure comprising a boron etch-stop layer on a surface of the integrated circuit structure having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon. In one embodiment, the boron etch-stop layer has a FWHM thickness value less than 20 nanometers and may contain added germanium or carbon. Systems and devices containing same are also disclosed. Chemical vapor deposition (CVD) may be used to form the boron etch-stop layer. | 10-02-2008 |
| 20090258478 | METHOD FOR PROVIDING A NANOSCALE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) ON INSULATOR - Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional embodiments are described. | 10-15-2009 |