Emmanouil Terrovitis, Foster City US
Emmanouil Terrovitis, Foster City, CA US
Patent application number | Description | Published |
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20130099762 | SYSTEMS AND METHODS FOR COUNTERACTING OVERVOLTAGE EVENTS - This disclosure involves methods and systems for reducing the voltage by a circuit such as a switching regulator during an overvoltage event by draining current from a voltage source when voltage exceeding a desired level is generated. | 04-25-2013 |
20130099763 | SYSTEMS AND METHODS FOR SUPPRESSING UNDESIRABLE LIMIT CYCLES IN SWITCHING REGULATORS - This disclosure involves methods and systems for suppressing undesired limit cycles in switching regulators by determining when a limit cycle causes the inductor to charge for a time greater than the clock period and destabilizing such cycles. | 04-25-2013 |
20130099870 | VOLTAGE CONTROLLED OSCILLATORS HAVING LOW PHASE NOISE - This disclosure involves systems for providing an oscillatory circuit having low phase noise featuring arrays of complementary VCO pairs connected in parallel. | 04-25-2013 |
20140002152 | CHARGE PUMP CIRCUIT | 01-02-2014 |
20140002198 | TWO-DELAY VOLTAGE-CONTROLLED-OSCILLATOR WITH WIDE TUNING RANGE | 01-02-2014 |
20140002205 | FREQUENCY SYNTHESIZER APPARATUS AND METHODS FOR IMPROVING CAPACITOR CODE SEARCH ACCURACY USING LSB MODULATION | 01-02-2014 |
20140003570 | FREQUENCY DIVIDER WITH IMPROVED LINEARITY FOR A FRACTIONAL-N SYNTHESIZER USING A MULTI-MODULUS PRESCALER | 01-02-2014 |
20140340132 | METHOD AND APPARATUS FOR GENERATING A REFERENCE SIGNAL FOR A FRACTIONAL-N FREQUENCY SYNTHESIZER - A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal. | 11-20-2014 |