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Emma, US
Anthony P. Emma, Sewell, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20100174838 | METHOD AND APPARATUS FOR EMPLOYING A SECOND BUS CONTROLLER ON A DATA BUS HAVING A FIRST BUS CONTROLLER - A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting patterns of the appearances preceding a qualifying quiet period on the data bus; a qualifying quiet period being a time interval having a duration greater than a predetermined duration with no traffic on the data bus; (c) employing the patterns to determine probability of occurrence of a qualifying quiet period following at least one pattern; and (d) permitting the second bus controller to control operation of the data bus during a respective qualifying quiet period when the probability of occurrence for the respective qualifying quiet period is greater than a predetermined value. | 07-08-2010 |
Dennis Emma, Gig Harbor, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20100137449 | SUBSTITUTED 1,3-CYCLOPENTADIONE MULTI-TARGET PROTEIN KINASE MODULATORS OF CANCER, ANGIOGENESIS AND THE INFLAMMATORY PATHWAYS ASSOCIATED THEREWITH - Compounds and methods for multi-targeted protein kinase modulation for angiogenesis, cancer treatment or the inflammatory pathways associated with those conditions are disclosed. The compounds and methods disclosed are based on substituted 1,3-cyclopentadione compounds. | 06-03-2010 |
Dennis A. Emma, Gig Harbor, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20100222262 | SUBSTITUTED 1, 3-CYCLOPENTADIONE ATTENUATED ENDOTHELIAL INFLAMMATION AND ENDOTHELIAL-MONOCYTE INTERACTIONS - Compositions and methods for reducing cardiovascular risk utilizing substituted 1,3-cyclopentadione compounds are described. | 09-02-2010 |
Philip Deorge Emma, Danburry, CT US
| Patent application number | Description | Published |
|---|---|---|
| 20080209126 | METHOD FOR ACHIEVING VERY HIGH BANDWIDTH BETWEEN THE LEVELS OF A CACHE HIERARCHY IN 3-DIMENSIONAL STRUCTURES, AND A 3-DIMENSIONAL STRUCTURE RESULTING THEREFROM - A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses. | 08-28-2008 |
Philip G. Emma, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100333056 | TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT - Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip. | 12-30-2010 |
Philip George Emma, Danbury, CT US
| Patent application number | Description | Published |
|---|---|---|
| 20080203445 | Three-Dimensional Cascaded Power Distribution in a Semiconductor Device - An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers. | 08-28-2008 |
| 20080215816 | APPARATUS AND METHOD FOR FILTERING UNUSED SUB-BLOCKS IN CACHE MEMORIES - A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests. | 09-04-2008 |
| 20080222358 | METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE - A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache. | 09-11-2008 |
| 20080229134 | RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM - In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing. | 09-18-2008 |
| 20090019341 | DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA - Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory. | 01-15-2009 |
| 20090198970 | METHOD AND STRUCTURE FOR ASYNCHRONOUS SKIP-AHEAD IN SYNCHRONOUS PIPELINES - An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate. | 08-06-2009 |
| 20110161780 | METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE - A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits. | 06-30-2011 |
Phillip Emma, Topsfield, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20090188911 | Multiple linked appliances with auxiliary outlet - A combination microwave and refrigerator system is constructed having a single plug input supply. The microwave oven is adapted to provide power to a refrigerator, and to auxiliary receptacles adapted for low power operation. The current to the low power receptacles and the refrigerator is controlled by the controller for the microwave oven according to the duty cycles of the connected appliances to avoid overload conditions. | 07-30-2009 |