Emirian
Frederic Emirian, Antony FR
Patent application number | Description | Published |
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20150135147 | Generating a Circuit Description for a Multi-die Field-programmable Gate Array - A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation. | 05-14-2015 |
20160048623 | Generating a Circuit Description for a Multi-Die Field-Programmable Gate Array - A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation. | 02-18-2016 |
Frédéric Emirian, Chilly-Mazarin FR
Patent application number | Description | Published |
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20100161306 | METHOD AND SYSTEM FOR EMULATING A DESIGN UNDER TEST ASSOCIATED WITH A TEST ENVIRONMENT - The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating ( | 06-24-2010 |
Frédéric Emirian, Chilly-Mazarin FR
Patent application number | Description | Published |
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20100161306 | METHOD AND SYSTEM FOR EMULATING A DESIGN UNDER TEST ASSOCIATED WITH A TEST ENVIRONMENT - The method of emulating the design under test associated with a test environment comprises two distinct generating phases comprising a first phase of generating ( | 06-24-2010 |
Frederic Maxime Emirian, Antony FR
Patent application number | Description | Published |
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20160098504 | EFFICIENT POWER ANALYSIS - Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number. | 04-07-2016 |