Ellersick

Steven D. Ellersick, Shoreline, WA US

Patent application number	Description	Published
20090251069	SYSTEMS AND METHODS FOR LIGHTING CONTROL IN FLIGHT DECK DEVICES - Systems and methods for illuminating flight deck devices are disclosed. In one embodiment, a flight deck panel illumination system includes at least one illuminated panel having at least one illumination source, and a power supply coupled to the at least one illumination source and to an electrical energy source that is configured to selectively provide a suitable power conversion mode in response to an applied signal. A processor is coupled to the power supply to generate the applied signal.	10-08-2009

Patent application number	Description	Published
20100073064	VOLTAGE CLAMP - An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.	03-25-2010

Patent application number	Description	Published
20100046693	LOW POWER RADIO FREQUENCY DIVIDER - In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop.	02-25-2010