Patent application number | Description | Published |
20080285659 | METHODS OF OPERATING A DUAL DECODER PORTABLE MEDIA DEVICE - Methods of operating a portable media device | 11-20-2008 |
20080285660 | DUAL DECODER PORTABLE MEDIA DEVICE - A portable media device | 11-20-2008 |
20090132763 | Memory Cards Having Two Standard Sets Of Contacts And A Hinged Contact Covering Mechanism - Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A cover that is hinged to the card to normally cover one set of contacts can be manually rotated out of the way when that set of contacts is being used. | 05-21-2009 |
20090134228 | MEMORY CARDS HAVING TWO STANDARD SETS OF CONTACTS AND A HINGED CONTACT COVERING MECHANISM - Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A cover that is hinged to the card to normally cover one set of contacts can be manually rotated out of the way when that set of contacts is being used. | 05-28-2009 |
20090286370 | Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements - Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate. | 11-19-2009 |
20100023800 | NAND Flash Memory Controller Exporting a NAND Interface - A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed. | 01-28-2010 |
20100047982 | Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element - A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers. | 02-25-2010 |
20100155784 | Three-Dimensional Memory Structures Having Shared Pillar Memory Cells - A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element. | 06-24-2010 |
20100169559 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 07-01-2010 |
20100169561 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 07-01-2010 |
20100205360 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 08-12-2010 |
20110041039 | Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device - The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of bad blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 02-17-2011 |
20110287619 | Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element - A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers. | 11-24-2011 |
20120135580 | Three-Dimensional Memory Structures Having Shared Pillar Memory Cells - A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element. | 05-31-2012 |
20130087623 | Universal Non-Volatile Memory Card Used with Various Different Standard Cards Containing a Memory Controller - A mother/daughter card non-volatile memory system includes a daughter card containing the memory and a mother card containing the memory controller and host interface circuits. The daughter memory card contains as little more than the memory cell array as is practical, in order to minimize its cost, and has an interface for connecting with a variety of mother controller cards having physical attributes and host interfaces according to a number of different published or proprietary memory card standards. Different types of memory cards may be used when the operating parameters of the memory are stored within it in a protected location, the mother card controller then reading these parameters and adapting its operation accordingly. A radio frequency antenna may be included on a surface of the card along with its electrical contacts, in order to provide a radio frequency identification function. | 04-11-2013 |
20130111113 | NAND Flash Memory Controller Exporting a NAND Interface | 05-02-2013 |
20140250348 | Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device - The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of had blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 09-04-2014 |