Patent application number | Description | Published |
20080230841 | INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER - An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region. | 09-25-2008 |
20090039388 | INTEGRATED CIRCUIT SYSTEM EMPLOYING A CONDENSATION PROCESS - An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer. | 02-12-2009 |
20090170268 | PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING EMBEDDED EPITAXIAL REGIONS - A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material. | 07-02-2009 |
20090203185 | METHOD FOR FABRICATING DEVICE STRUCTURES HAVING A VARIATION IN ELECTRICAL CONDUCTIVITY - A method for forming device structures having a variation in electrical conductivity includes forming a device structure and a radiation absorbing layer overlying the device structure. The radiation absorbing layer has a spatial variation and radiation absorbing characteristics, such that upon irradiating the device structure, the radiation absorbing layer attenuates the intensity of the radiation so that a variation in dopant activation takes place within the device structure. Accordingly, device structures are formed having a variation in electrical resistance independent of the physical size of the device structures. | 08-13-2009 |
20090218636 | INTEGRATED CIRCUIT SYSTEM FOR SUPPRESSING SHORT CHANNEL EFFECTS - An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening. | 09-03-2009 |
20090221117 | INTEGRATED CIRCUIT SYSTEM EMPLOYING RESISTANCE ALTERING TECHNIQUES - An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device. | 09-03-2009 |
20090246920 | METHODS FOR NORMALIZING STRAIN IN A SEMICONDUCTOR DEVICE - The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density. | 10-01-2009 |
20090280629 | INTEGRATED CIRCUIT SYSTEM EMPLOYING GRAIN SIZE ENLARGEMENT - An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a dopant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the substrate; and annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device. | 11-12-2009 |
20100230765 | INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER - An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization. | 09-16-2010 |
20100304556 | INTEGRATED CIRCUIT SYSTEM WITH VERTICAL CONTROL GATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa. | 12-02-2010 |
20120070971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING - There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions. | 03-22-2012 |
20140239371 | FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE - Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer. | 08-28-2014 |
20140264554 | BACK-GATED NON-VOLATILE MEMORY CELL - A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate. | 09-18-2014 |