El-Moursy
Ali El-Moursy, Giza EG
Patent application number | Description | Published |
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20110004883 | Method and System for Job Scheduling - Logical processors/hardware contexts are assigned to different jobs/threads in a multithreaded/multicore environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a super-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. The judgement of satisfactory performance is preferably based on the difference between a desired number of time quantum attributed per super-context switch interval to each job/thread and a real number of time quantum attributed per super-context switch interval to each job/thread. | 01-06-2011 |
Ali El-Moursy, Gizi EG
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20100162041 | FETCH OPERATION SCHEDULING - Fetch operations are assigned to different threads in a multithreaded environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a sub-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. Two-level priority scheme is used to combine both priorities. The judgement of satisfactory performance is preferably based on the difference between a desired number of fetch operations attributed per sub-context switch interval to each thread and a real number of fetch operations attributed per sub-context switch interval to each thread. | 06-24-2010 |
Ali A. El-Moursy, Cairo EG
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20100023728 | METHOD AND SYSTEM FOR IN-PLACE MULTI-DIMENSIONAL TRANSPOSE FOR MULTI-CORE PROCESSORS WITH SOFTWARE-MANAGED MEMORY HIERARCHY - A method and system for transposing a multi-dimensional array for a multi-processor system having a main memory for storing the multi-dimensional array and a local memory is provided. One implementation involves partitioning the multi-dimensional array into a number of equally sized portions in the local memory, in each processor performing a transpose function including a logical transpose on one of said portions and then a physical transpose of said portion, and combining the transposed portions and storing back in their original place in the main memory. | 01-28-2010 |
Ali A. El-Moursy, Dokki EG
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20120192195 | SCHEDULING THREADS - Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window. | 07-26-2012 |
Ali A. El-Moursy, Giza EG
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20140149990 | SCHEDULING THREADS - Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window. | 05-29-2014 |