| Patent application number | Description | Published |
|---|
| 20090153401 | MOTION DETECTION FOR TRACKING - An apparatus and method for tracking a target wherein a new position fix is taken when the measured movement of the target is more than a predetermined threshold amount or when the position fix has not been updated in a predetermined interval. The apparatus and method minimize energy use and network resources by performing position determination fixes only when needed. | 06-18-2009 |
| 20100090852 | GEOGRAPHICAL BOUNDARY BASED TRACKING - An apparatus, method and system for geographical tracking entry and/or exiting of an asset into and/or out of a defined geographical boundary and reporting the same. Entry and exit tests compare position fixes with various thresholds and parameters to determine if the asset has entered or exited the geographical boundary. Tests are sequenced such that tests having lower levels of complexity (lower order) are performed before tests having higher levels of complexity (higher order). In this way, most position fixes are processed using computations having a lower order of mathematical complexity than conventionally implemented. | 04-15-2010 |
| 20100098135 | METHOD AND APPARATUS FOR AVOIDING INTERFERENCE BETWEEN COEXISTING WIRELESS SYSTEMS - Apparatuses and methods for avoiding interference between wireless systems are described herein. One embodiment of the disclosure provides an apparatus for avoiding interference between at least one transmitter and at least one receiver within at least one wireless device. The apparatus comprises a first processing circuit configured to determine whether one or more bins are affected by interference from a transmitter based on predetermined information. The apparatus further comprises a second processing circuit configured to mitigate the interference from the transmitter by at least one of the transmitter and a receiver if it is determined that the one or more bins are affected | 04-22-2010 |
| 20100250134 | DEAD RECKONING ELEVATION COMPONENT ADJUSTMENT - The subject matter disclosed herein relates to adjusting an elevation component of a estimated location based, at least in part, on sensor-based dead reckoning. | 09-30-2010 |
| 20100284424 | SYSTEM AND METHOD FOR ADAPTING TRANSMIT DATA BLOCK SIZE AND RATE BASED ON QUALITY OF COMMUNICATION LINK - System and method for transmitting data to a remote communication device to achieve desirable transmit data block size and data rate based on measurements of the communication link quality to the remote device. The method entails selecting an initial transmit data rate and power based on an initial measurement of the link quality, and a default size for the transmit data block. The data block is then transmitted to the remote, and an acknowledgement (ACK) message is received from the remote. If the ACK message indicates that the data block was properly received, the size for the next data block to be transmitted is increased. Otherwise, the size for the next data block may be decreased or remain the same. Additionally, the transmit data rate may be increased if the remote properly receives a defined number of consecutive data blocks, or decreased if the remote does not receive a defined number of consecutive data blocks. | 11-11-2010 |
| Patent application number | Description | Published |
|---|
| 20090164763 | METHOD AND APPARATUS FOR A DOUBLE WIDTH LOAD USING A SINGLE WIDTH LOAD PORT - A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load. | 06-25-2009 |
| 20090172355 | INSTRUCTIONS WITH FLOATING POINT CONTROL OVERRIDE - Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described. | 07-02-2009 |
| 20090172358 | IN-LANE VECTOR SHUFFLE INSTRUCTIONS - In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand. | 07-02-2009 |
| 20090172363 | MIXING INSTRUCTIONS WITH DIFFERENT REGISTER SIZES - When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers. | 07-02-2009 |
| 20090172365 | Instructions and logic to perform mask load and store operations - In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed. | 07-02-2009 |
| 20090265409 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 10-22-2009 |
| 20110093682 | METHOD AND APPARATUS FOR PACKING DATA - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element. | 04-21-2011 |
| 20110153707 | MULTIPLYING AND ADDING MATRICES - An apparatus and method are described for multiplying and adding matrices. For example, one embodiment of a method comprises decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein each vector represents an m-by-m matrix of data elements and m is greater than one; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a resultant vector, wherein the resultant vector represents an m-by-m matrix of data elements. | 06-23-2011 |
