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Eisner
Cindy Eisner, Haifa IL
| Patent application number | Description | Published |
|---|---|---|
| 20100325596 | CLOCK GATING USING ABSTRACTION REFINEMENT - An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design. | 12-23-2010 |
Cynthia Rae Eisner, Yaacov IL
| Patent application number | Description | Published |
|---|---|---|
| 20090064064 | Device, System and Method for Formal Verification - Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement that uses a deterministic automaton. The deterministic automaton is exponential in the size of the input property. The assume verification directive may be transformed into a strong suffix implication in the property specification language. | 03-05-2009 |
Cynthia Rae Eisner, Zichron Yaacov IL
| Patent application number | Description | Published |
|---|---|---|
| 20080301604 | APPARATUS FOR AND METHOD OF ESTIMATING THE QUALITY OF CLOCK GATING SOLUTIONS FOR INTEGRATED CIRCUIT DESIGN - A novel apparatus for and method of estimating the quality of candidate clock gating solutions. The quality estimation mechanism of the present invention filters candidate clock gating solutions by estimating a measure of the quality of each candidate solution. The effect of the proposed solution on both timing and leakage power is considered by determining the intersection coefficient for each candidate clock gating solution. The intersection coefficient (IC) is the number of signals shared by both the data logic portion and clock enable logic portions of a proposed clock gating solution. Only those proposed solutions whose IC value is less than or equal to a threshold are considered as possible clock gating solutions. The IC value functions as a reliable predictor of whether a candidate clock gating solution is a good solution without requiring complex heavy analyses that would normally be applied to the final circuit design. | 12-04-2008 |
| 20090013289 | CIRCUIT DESIGN OPTIMIZATION OF INTEGRATED CIRCUIT BASED CLOCK GATED MEMORY ELEMENTS - A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of duplicate unclock gated memory elements is then effected by identifying identical danonical representations of said unclock gated memory elements. Identified duplicate clock gated memory elements can then be eliminated from the original digital circuit. Further optimization can be accomplished by applying standard logic optimization algorithms to all unclock gated memory elements in said digital circuit. The resulting optimized circuit is clock gated and replaces the original clock gated circuit in said digital circuit. | 01-08-2009 |
| 20090044154 | OVER APPROXIMATION OF INTEGRATED CIRCUIT BASED CLOCK GATING LOGIC - A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function. | 02-12-2009 |
| 20100017764 | FUNCTIONAL VERIFICATION OF POWER GATED DESIGNS BY COMPOSITIONAL REASONING - A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. A compositional approach is first used to look for conditional equivalence of each functional block of the circuit (and its corresponding functional block with power gating disabled) under a suitable set of assumptions, guaranteed by the neighboring functional blocks. Circular reasoning rules are then employed to compose the conditional equivalences proved on the individual functional blocks back into total equivalence on the whole circuit. | 01-21-2010 |
Cynthia Rae Eisner, Zichron Ya'Akov IL
| Patent application number | Description | Published |
|---|---|---|
| 20110010679 | METHOD FOR MULTI-CYCLE CLOCK GATING - An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The circuit design updater updates the circuit design with selected multi-cycle gating groups. Each gating group is associated with a single gating function. For each gating group, data latching devices of 0 | 01-13-2011 |
Jurgen Eisner, Maintal DE
Leo Eisner, Praha CZ
| Patent application number | Description | Published |
|---|---|---|
| 20110069584 | METHOD OF LOCATING A RECEIVER IN A WELL - A microseismic method of determining the position of a downhole receiver ( | 03-24-2011 |
Leo Eisner, Prague CZ
| Patent application number | Description | Published |
|---|---|---|
| 20090296525 | NOISE SUPPRESSION FOR DETECTION AND LOCATION OF MICROSEISMIC EVENTS USING A MATCHED FILTER - A method for determining presence of seismic events in seismic signals includes determining presence of at least one seismic event in seismic signals corresponding to each of a plurality of seismic sensors. A correlation window is selected for each of the plurality of seismic signals. Each correlation window has a selected time interval including an arrival time of the at least one seismic event in each seismic signal. Each window is correlated to the respective seismic signal between a first selected time and a second selected time. Presence of at least one other seismic event in the seismic signals from a result of the correlating. | 12-03-2009 |
Leo Eisner, Cambridge GB
| Patent application number | Description | Published |
|---|---|---|
| 20090048783 | METHOD FOR MONITORING SEISMIC EVENTS - A microseismic method of monitoring fracturing operation or other microseismic events in hydrocarbon wells is described using the steps of obtaining multi-component signal recordings from a single monitoring well in the vicinity of a facture or event; and rotating observed signals such that they become independent of at least one component of the moment tensor representing the source mechanism and performing an inversion of the rotated signals to determine the remaining components. | 02-19-2009 |
Matthias Eisner, Neukirchen DE
| Patent application number | Description | Published |
|---|---|---|
| 20110308928 | Switch, In Particular Switch Disconnector For Low Voltages - A switch is disclosed, in particular a switch disconnector for low voltages, including at least one cuboid pole housing; a switching shaft which runs transversely with respect to the side walls and disconnects contact elements which are resting on one another in order to open the switch; and an aperture opening formed in one wall of the pole housing. In order to prevent the risk of an electrical flashover to the rear wall, it is proposed in at least one embodiment, that the aperture opening is formed in a side wall, to which a channel is connected, which dissipates any overpressure that occurs in the pole housing in an end-face outlet direction. | 12-22-2011 |
Matthias Eisner, Enkirchen DE
| Patent application number | Description | Published |
|---|---|---|
| 20110318126 | MACHINE DEVICE AND METHOD FOR ENSURING A PREDETERMINED MACHINING DEPTH - The invention relates to a machining device for machining a workpiece (W), wherein a rotatably mounted machining tool ( | 12-29-2011 |
| 20110320031 | MACHINING DEVICE FOR MACHINING A WORKPIECE - The invention relates to a machining device for machining a workpiece, wherein a rotatably mounted machining tool ( | 12-29-2011 |
Stanimir Eisner, Russe BG
| Patent application number | Description | Published |
|---|---|---|
| 20120036458 | AUTOMATIC CONTEXT PASSING DURING MANAGEMENT APPLICATION NAVIGATION - Various embodiments of systems and methods for automatic context passing during management application navigation are described herein. When management applications work with different managed entities, the managed context is preserved by following the relations between the managed entities. These relations are followed from a mediator framework during the navigation between the management applications. In this manner, a managed application passes context information for one entity type, and second managed application retrieves from the framework context information for different entity type, but the user context information will be preserved as the framework follows the relations between the passed entity and the requested entity types. | 02-09-2012 |