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Eisenstadt
Marc Eisenstadt, Milton Keynes GB
| Patent application number | Description | Published |
|---|---|---|
| 20090077221 | SYSTEM FOR ANALYZING AND VISUALIZING ACCESS STATISTICS FOR A WEB SITE - A method for monitoring and visualizing user access made to a web site is disclosed. The method comprises: embedding in a web page to be monitored code to request a thumbnail image from a site when the page is loaded into a browser. The embedded code also includes a user-activateable link to a page within the system server. At the system server, the requested thumbnail image is returned to the web browser, and the IP address from which the thumbnail was requested is recorded. For each recorded IP address, the server determines a corresponding geographical location. The server creates and stores an image that is a geographical representation of the geographical distribution of the recorded IP addresses, and a thumbnail representation of that image. Upon activation of the user-activateable link, the linked page within the system server that includes the image previously created is retrieved by the browser. The thumbnail image requested by the embedded code is the thumbnail image created in this step. A number of threshold, updating, clustering, storage and archiving routines are deployed to ensure large scalability. | 03-19-2009 |
Robert Eisenstadt, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110260318 | Integrated circuits with multiple I/O regions - Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages. | 10-27-2011 |
William R. Eisenstadt, Gainesville, FL US
| Patent application number | Description | Published |
|---|---|---|
| 20080309321 | Distributed Rf/Microwave Power Detector - A distributed RF/microwave power detector for detecting the power of a signal is provided. The distributed RF/microwave power detector includes a power detector on or at least partially embedded in a single substrate. The distributed RF/microwave power detector includes a detection unit that has a distributed amplifier for amplifying the signal and outputting an amplified signal, and a detector for detecting the power of the amplified signal. The distributed RF/microwave power detector further includes at least one additional detection unit cascaded with the first. The additional detection unit includes an additional distributed amplifier for amplifying the amplified signal and outputting a further amplified signal, as well as an additional detector for detecting a power of the further amplified signal. The distributed RF/microwave power detector also includes a multiplexer for multiplexing outputs of the detector and at least one additional detector, each having a dynamic range different from the other. | 12-18-2008 |
| 20090005103 | EMBEDDED IC TEST CIRCUITS AND METHODS - A self-testing transceiver having an on-chip power detection capability is provided. The self-testing transceiver can include a semiconductor substrate and a transmitter having a high-power amplifier disposed on the substrate. The self-testing transceiver also can include a receiver disposed on the substrate for selectively coupling to an antenna. The self-testing transceiver can further include at least one power detector disposed on the semiconductor substrate for determining a power such as an RMS and/or peak-power of a signal at an internal node of the self-testing transceiver. Additionally, the self-testing transceiver can include a loopback circuit disposed on the substrate. | 01-01-2009 |
| 20090125772 | WIRELESS EMBEDDED TEST SIGNAL GENERATION - An RF/Microwave on-chip signal source for testing an integrated circuit embedded in a substrate is provided. The signal source includes an on-chip antenna embedded in the substrate to receive a signal from a signal source external to the substrate. The signal source also includes a frequency divider circuit also embedded in the substrate. The frequency divider converts one or more frequencies of the signal into an operating frequency of the integrated circuit, the signal at the operating frequency of the integrated circuit defining an on-chip test signal. The signal source further includes one or more output buffers embedded in the substrate to provide a signal interface with the integrated circuit. | 05-14-2009 |
| 20100145651 | SELF-CALIBRATION SYSTEMS AND METHODS - Various embodiments of self-calibration systems and methods are described. One method embodiment, among others, includes imposing an alternate test to components within the device, responsive to the imposition of the alternate test, providing test responses corresponding to the components, and substantially, simultaneously mapping each of the test responses to corresponding specification values of the components. | 06-10-2010 |
William Richard Eisenstadt, Gainesville, FL US
| Patent application number | Description | Published |
|---|---|---|
| 20100097154 | Broadband Active Balun - A broadband active balun configuration is provided. According to embodiments, the subject active balun can include a cascade and cascade transistor pair using a shared input transistor. In a further implementation, a low-pass bias-feedback mechanism for maintaining stable bias conditions can be provided. | 04-22-2010 |
| 20100327940 | EMBEDDED PHASE NOISE MEASUREMENT SYSTEM - Phase noise detection systems for a device under test (DUT) are provided that can be embedded within a chip. According to one embodiment, the embedded phase noise detection system can include an active delay line cell, a phase shifter, and a phase detector. The active delay line and phase shifter separately receive the output signal of the DUT. The phase detector can include a double-balanced mixer followed by an active RC filter. The double-balanced mixer receives, as input, the outputs from the active delay line and phase shifter and can produce different dc voltages proportional to the difference from the input phase quadrature. An auto-adjustment circuit can also be included to help the input signal from the phase shifter to the mixer maintain quadrature. | 12-30-2010 |