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Eiji Ito
Eiji Ito, Kawasaki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110006424 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material. | 01-13-2011 |
Eiji Ito, Nagano-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100306584 | CONTROLLER AND CONTROL METHOD FOR A CONTROLLER - A controller and a control method for a controller can simplify application development and can improve the performance of device control processes. When a request is received from an application | 12-02-2010 |
Eiji Ito, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20100038617 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction. | 02-18-2010 |
| 20100248431 | METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE - A method for manufacturing a nonvolatile storage device including: a plurality of first electrodes aligning in a first direction; a plurality of second electrodes aligning in a second direction nonparallel to the first direction and provided above the first electrodes; and a first storage unit provided between the first electrode and the second electrode and including a first storage layer, a resistance of the first storage layer changing by at least one of an applied electric field and an applied current, the method includes: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a major surface of a substrate; processing the first electrode film and the first storage unit film into a strip shape aligning in the first direction; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the sacrifice layer; forming a mask layer having a lower etching rate than the sacrifice layer on the second electrode film; processing the second electrode film into a strip shape aligning in the second direction nonparallel to the first direction by using the mask layer as a mask; removing a portion of the first storage unit film exposed from the sacrifice layer by using the mask layer as a mask to process the first storage unit film into a columnar shape including a side wall along the first direction and a side wall along the second direction; removing the sacrifice layer to expose the first storage unit film having been covered with the sacrifice layer; and removing the exposed first storage unit film. | 09-30-2010 |
Eiji Ito, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090134432 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers. | 05-28-2009 |
| 20090212352 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 08-27-2009 |
| 20090251940 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE USING A VARIABLE RESISTANCE FILM AND METHOD OF MANUFACTURING THE SAME - A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes. | 10-08-2009 |
| 20100038616 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCING METHOD THEREOF - A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction. | 02-18-2010 |
| 20110147822 | Semiconductor memory device and method for manufacturing the same - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 06-23-2011 |
Eiji Ito, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090033592 | PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF - A plasma display device including a scan circuit, a plasma display panel, and a plurality of power sources for driving the plasma display panel. The scan circuit is configured to apply scan voltages to scan electrodes of the plasma display panel in order to select light-emitting cells and non-light-emitting cells during an address period. The scan circuit includes a capacitor configured to remove the need to provide a current cut-off switch to prevent undesirable current flowing between the power supplies during the operation of the plasma display. | 02-05-2009 |