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Ehud Cohen

Ehud Cohen, Kiryat Motskin IL

Patent application numberDescriptionPublished
20090164763METHOD AND APPARATUS FOR A DOUBLE WIDTH LOAD USING A SINGLE WIDTH LOAD PORT - A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.06-25-2009
20090300319APPARATUS AND METHOD FOR MEMORY STRUCTURE TO HANDLE TWO LOAD OPERATIONS - An apparatus and method to increase memory bandwidth is presented. In one embodiment, the apparatus comprises a load array having: a first array to store a plurality of load operation entries and a second array to store a second plurality of load operation entries. The apparatus further comprises: a store array having a plurality of store operation entries; a first address generation unit coupled to send a linear address of a first load operation to the first array and to send a linear address of a first store operation to the store array; and a second address generation unit coupled to send a linear address of a second load operation to the second array and to send a linear address of a second store operation to the store array.12-03-2009
20100161907POSTING WEAKLY ORDERED TRANSACTIONS - A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.06-24-2010
20100169382METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE - A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.07-01-2010
20100169579READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.07-01-2010
20100169580MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.07-01-2010

Patent applications by Ehud Cohen, Kiryat Motskin IL

Ehud Cohen, Kirvat Motskin IL

Patent application numberDescriptionPublished
20100169581EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA - A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.07-01-2010

Ehud Cohen, Motskin IL

Patent application numberDescriptionPublished
20100146212Accessing a cache memory with reduced power consumption - In one embodiment, a cache memory includes a data array having N ways and M sets and at least one fill buffer coupled to the data array, where the data array is segmented into multiple array portions such that only one of the portions is to be accessed to seek data for a memory request if the memory request is predicted to hit in the data array. Other embodiments are described and claimed.06-10-2010

Ehud Cohen, San Diego, CA US

Patent application numberDescriptionPublished
20090208960METHODS FOR IDENTIFYNG CELLULAR MODULATORS OF DISAGGREGATION ACTIVITY OR AGGREGATION ACTIVITY IN AN ANIMAL - Methods for identifying a cellular modulator of a biological disaggregation activity or a biological aggregation activity of an animal are provided. Methods for identifying a compound which modulates biological disaggregation activity or a biological aggregation activity in a biological sample are provided.08-20-2009

Ehud Cohen, Tel Aviv IL

Patent application numberDescriptionPublished
20090070236Diamond and Precious Stone Trading Platform with Funding and Delivery Transparency - The transparent diamond and precious stone trading platform and method has funding and delivery transparency during the buy-order, funding, and tracking pickup, independent comparative inspection, and final delivery of each stone. The database of stones includes, for each stone, stone-weight, stone characteristics, price, and a grading lab certificate. The certificate uniquely identifies each stone and is electronically accessible by sellers, buyers, couriers, and authentication services. A buy command is communicated to seller and buyer. The transfer funds is electronically noted and communicated. The pickup by courier, interim delivery, inspection comparing the stone to the certificate, and subsequent delivery to buyer and release of funds is communicated to traders by emails, text messages, automated voice messages or IVR. Buyer and seller profiles establish communications channels and organizational managers are also permitted access and given communications. If time or place parameters are exceeded, increasing levels of alarm electronic communications are implemented.03-12-2009
20090125435Trading Plaftorm System and Method for Diamond and Precious Stone Transactions - The transaction method and system facilitates sales of diamonds or stones. A searchable database of stones includes, for each stone, an offer to sell, a weight-carat, other stone characteristics and an electronic copy of a grading lab certificate which uniquely identifies each stone from all other stones in the database. A search displays, for each stone, the offer and stone weight, stone characteristics and electronic access to the stone's certificate. The system permits a prospective buyer to “buy now,” which closes the transaction at the posted offer, or “bid now” wherein the system logs a bid value and an expiry time. Other bids are posted and displayed, in a primacy order until (a) the seller “buy now at the bid” or (b) withdraws the offer or (c) replaces the offer with a subsequent offer. Preferably, offers: displayed in time sequence and bids: displayed by primacy of price and expiry.05-14-2009

Ehud Cohen, Ganei Tivka IL

Patent application numberDescriptionPublished
20090005845Intra-Atrial parasympathetic stimulation - A method is provided, including implanting in an atrial wall of a subject, from within an atrium, a first electrode contact in a vicinity of a parasympathetic epicardial fat pad of the subject, and implanting a second electrode contact in a body of the subject outside of a heart and a circulatory system. A current is driven between the first and second electrode contacts, and configured to cause parasympathetic activation of the fat pad. Other embodiments are also described.01-01-2009

Ehud Cohen, Rehovot IL

Patent application numberDescriptionPublished
20110138487Storage Device and Method for Using a Virtual File in a Public Memory Area to Access a Plurality of Protected Files in a Private Memory Area - A storage device and method for using a virtual file in a public memory area to access a plurality of protected files in a private memory area are disclosed. In one embodiment, a storage device receives a request from a host for access to a virtual file in the public memory area, wherein the virtual file is associated with a plurality of protected files stored in the private memory area. The storage device responds to the request by selecting and providing the host with access to one of the plurality of protected files stored in the private memory area. The storage device receives an additional request from the host for access to the virtual file and responds to the additional request by selecting and providing the host with access to a different one of the plurality of protected files stored in the private memory area.06-09-2011

Ehud Cohen, Kiryat IL

Patent application numberDescriptionPublished
20110320723METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE - A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.12-29-2011