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Ehrenreich, DE
Hannelore Ehrenreich, Gottingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20090022734 | USE OF EPO RECEPTOR ACTIVATION OR STIMULATION FOR THE IMPROVEMENT OF THE EDSS SCORE IN PATIENTS WITH MULTIPLE SCLEROSIS - The invention provides a method of improving the expanded disability status scale (EDSS) score achieved by mammals affected by multiple sclerosis in which a substance effecting increased and/or prolonged activation and/or stimulation of the erythropoietin (EPO) receptor is administered to the mammal. In certain embodiments, the substance is administered in intervals which are interrupted by application-free periods of time in which said substance is not administered. | 01-22-2009 |
| 20090036359 | Use of erythropoietin and substances increasing and/or prolonging the activation and/or stimulation of erythropoietin receptors for treating and/or preventing schizophrenia and related psychoses - Method for treatment and/or prophylaxis of schizophrenia and related psychoses of a human being, erythropoietin being administered to the human being. | 02-05-2009 |
Hannelore Ehrenreich, Goettingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20080206881 | DIAGNOSTIC MARKER FOR NEURODEGENERATIVE DISEASES - For neurodegenerative diseases such as amyotrophic lateral sclerosis the prediction of disease progression or response to therapy based on phenotypic parameters is very difficult and inaccurate. The measurement of the serum protein carbonyl content allows a quantitative and early diagnosis of these diseases. It enables the monitoring of the disease progression as well as the individual adjustment of the therapy. Furthermore, this diagnostic marker can be used as a readout in animal model based screening methods for new therapeutic approaches and compounds. | 08-28-2008 |
| 20110112018 | Method for the Treatment and/or Prophylaxis of Multiple Sclerosis, and Use of Erythropoietin for the Manufacture of a Medicament for the Intermittent and/or Intermittent Prophylaxis of Multiple Sclerosis - The present invention relates to a method for the treatment and/or prophylaxis of multiple sclerosis, and to the use of erythropoietin for this purpose and for the manufacture of a medicament for the intermittent treatment and/or intermittent prophylaxis of multiple sclerosis. | 05-12-2011 |
Sebastian Ehrenreich, Boeblingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100237700 | Signal Repowering Chip For 3-Dimensional Integrated Circuit - A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level. | 09-23-2010 |
| 20100309734 | METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVICE FOR MONITORING MEMORY CIRCUITS AND CORRESPONDING INTEGRATED CIRCUIT - An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected. | 12-09-2010 |
Sebastian Ehrenreich, Schoenau DE
| Patent application number | Description | Published |
|---|---|---|
| 20080256413 | Redundancy in Signal Distribution Trees - A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees ( | 10-16-2008 |
| 20080273403 | STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING AND CELL ACCESS DETECTION CIRCUIT - A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution. | 11-06-2008 |
| 20090059688 | Single-ended read and differential write scheme - A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read. | 03-05-2009 |
| 20090154263 | DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT - A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. | 06-18-2009 |
| 20090285046 | METHOD TO REDUCE LEAKAGE OF A SRAM-ARRAY - A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode. | 11-19-2009 |