Patent application number | Description | Published |
20090083551 | DYNAMICALLY MANAGING THERMAL LEVELS IN A PROCESSING SYSTEM - A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable. | 03-26-2009 |
20090172375 | Operating Point Management in Multi-Core Architectures - Systems and methods of managing operating points provide for determining the number of active cores in a plurality of processor cores. A maximum operating point is selected for at least one of the active cores based on the number of active cores. In one embodiment, the number of active cores is determined by monitoring an ACPI processor power state signal of each of the plurality of cores. | 07-02-2009 |
20090217070 | Dynamic Bus Parking - Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to the power saving message. In one embodiment, the power saving message is issued by de-asserting a bus arbitration signal and the power saving activity can include disabling one or more input buffers of the controller. | 08-27-2009 |
20090322409 | Power reduction apparatus and method - Provided is an approach to saving active power through lowering a supply voltage when operating temperature goes up, while substantially maintaining operating performance. | 12-31-2009 |
20100064162 | TECHNIQUES TO MANAGE OPERATIONAL PARAMETERS FOR A PROCESSOR - Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical characteristics for multiple components of a computing platform, and managing a performance level for a processor based on the performance values and one or more operational parameters for the processor. The operational parameters may include one or more transitory operational parameters that cause the processor to temporarily exceed operational parameters set by a thermal design power limit. Other embodiments are described and claimed. | 03-11-2010 |
20100083009 | POWER MANAGEMENT FOR PROCESSING UNIT - Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed. | 04-01-2010 |
20100102949 | OVERHEAT DETECTION IN THERMALLY CONTROLLED DEVICES - Systems and methods of overheat detection provide for generating a control signal on a die containing a processor based on an internal temperature of the processor and a control temperature threshold. It can be determined whether to generate a warning temperature event on the die based on a behavior of the control signal. In one embodiment, the warning temperature event provides for initiation of an automated data saving process, which reduces the abruptness of conventional warning temperature shutdowns. Other embodiments provide the user the option of saving his or her work before a shutdown temperature threshold is reached. | 04-29-2010 |
20100115293 | DETERMINISTIC MANAGEMENT OF DYNAMIC THERMAL RESPONSE OF PROCESSORS - Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed. | 05-06-2010 |
20100115304 | POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES - Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed. | 05-06-2010 |
20100162023 | METHOD AND APPARATUS OF POWER MANAGEMENT OF PROCESSOR - A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy. | 06-24-2010 |
20100169609 | Method for optimizing voltage-frequency setup in multi-core processor systems - A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode. | 07-01-2010 |
20100205464 | METHOD AND APPARATUS FOR ON-DIE TEMPERATURE SENSING AND CONTROL - For one disclosed embodiment, a plurality of processor cores may be on a semiconductor die. The processor cores may have at least one corresponding temperature sensor. Circuitry on the semiconductor die may generate thermal event indications based on sensed temperatures from multiple temperature sensors of multiple processor cores. A thermal event indication may indicate that a sensed temperature exceeds a temperature point. Central management logic on the semiconductor die may receive thermal event indications based on sensed temperatures from multiple temperature sensors of multiple processor cores. The central management logic may modify operation of one or more of the processor cores in response to a thermal event indication. Other embodiments are also disclosed. | 08-12-2010 |
20110099397 | OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES - For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. Other embodiments are also disclosed. | 04-28-2011 |
20120166839 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE - Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state. | 06-28-2012 |
20120166854 | Controlling Current Transients In A Processor - In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed. | 06-28-2012 |
20120185709 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING THREAD CONSOLIDATION - An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment. | 07-19-2012 |
20120204042 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 08-09-2012 |
20120221873 | Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices - According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device. | 08-30-2012 |
20120254641 | APPARATUS AND METHOD FOR HIGH CURRENT PROTECTION - An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded. | 10-04-2012 |
20120254643 | Managing Power Consumption In A Multi-Core Processor - A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3 | 10-04-2012 |
20130054179 | Determining An Effective Stress Level On A Processor - In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed. | 02-28-2013 |
20130061064 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 03-07-2013 |
20130080803 | Estimating Temperature Of A Processor Core In A Low Power State - In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed. | 03-28-2013 |
20130080804 | Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed. | 03-28-2013 |
20130111120 | Enabling A Non-Core Domain To Control Memory Bandwidth | 05-02-2013 |
20130111121 | Dynamically Controlling Cache Size To Maximize Energy Efficiency | 05-02-2013 |
20130111226 | Controlling A Turbo Mode Frequency Of A Processor | 05-02-2013 |
20130111236 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor | 05-02-2013 |
20130151569 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 06-13-2013 |
20130173941 | Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed. | 07-04-2013 |
20130173946 | CONTROLLING POWER CONSUMPTION THROUGH MULTIPLE POWER LIMITS OVER MULTIPLE TIME INTERVALS - Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed. | 07-04-2013 |
20130179704 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 07-11-2013 |
20130179705 | Controlling A Turbo Mode Frequency Of A Processor - In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. | 07-11-2013 |
20130179706 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 07-11-2013 |
20130179709 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed. | 07-11-2013 |
20130219196 | POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES - Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed. | 08-22-2013 |
20130232368 | MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR - A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3 | 09-05-2013 |
20130275737 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130275796 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130283032 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-24-2013 |
20140006758 | Extension of CPU Context-State Management for Micro-Architecture State | 01-02-2014 |
20140006808 | EFFICIENT INTEGRATED SWITCHING VOLTAGE REGULATOR | 01-02-2014 |
20140040643 | METHOD AND APPARATUS OF POWER MANAGMENT OF PROCESSOR - A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy. | 02-06-2014 |
20140082630 | PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM - In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed. | 03-20-2014 |
20140095905 | Computing System and Processor With Fast Power Surge Detection And Instruction Throttle Down To Provide For Low Cost Power Supply Unit - A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor. | 04-03-2014 |
20140095911 | Controlling Power Consumption By Power Management Link - Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed. | 04-03-2014 |
20140115351 | DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 04-24-2014 |
20140115362 | OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES - For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed. | 04-24-2014 |
20140129808 | MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR - In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed. | 05-08-2014 |
20140189376 | TOTAL PLATFORM POWER CONTROL - Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed. | 07-03-2014 |
20140245034 | MULTI-LEVEL CPU HIGH CURRENT PROTECTION - Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed. | 08-28-2014 |
20140281634 | CONTROLLING POWER SUPPLY UNIT POWER CONSUMPTION DURING IDLE STATE - Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g. S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed. | 09-18-2014 |
20140317422 | Method And Apparatus To Control Current Transients In A Processor - In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed. | 10-23-2014 |
20140325184 | MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT - A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data. | 10-30-2014 |
20140344598 | Enabling A Non-Core Domain To Control Memory Bandwidth - In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed. | 11-20-2014 |
20140380076 | Mapping A Performance Request To An Operating Frequency In A Processor - In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed. | 12-25-2014 |
20140380081 | Restricting Clock Signal Delivery In A Processor - In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed. | 12-25-2014 |
20140380338 | Method And Apparatus To Protect A Processor Against Excessive Power Usage - In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed. | 12-25-2014 |