| Patent application number | Description | Published |
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| 20080254632 | Method for forming a semiconductor structure having nanometer line-width - A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed. | 10-16-2008 |
| 20090267201 | Vertical Transmission Structure - A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core. | 10-29-2009 |
| 20100129956 | Method for forming a GexSi1-x buffer layer of solar-energy battery on a silicon wafer - The method is disclosed that Si | 05-27-2010 |
| 20100248430 | High Frequency Flip Chip Package Process of Polymer Substrate and Structure thereof - In a high frequency flip chip package process of a polymer substrate and a structure thereof, the structure is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost. | 09-30-2010 |
| 20110089467 | OHMIC CONTACT OF III-V SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Heavily doped epitaxial SiGe material or epitaxial In | 04-21-2011 |
| 20110121923 | VERTICAL TRANSMISSION STRUCTURE - A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core. | 05-26-2011 |
| 20110156100 | High Electron Mobility Transistor and Method for Fabricating the Same - A high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a spacer layer, a schottky layer and a cap layer. The buffer layer is formed on the substrate. The channel layer is formed on the buffer layer, in which the channel layer comprises a superlattice structure formed with a plurality of indium gallium arsenide thin films alternately stacked with a plurality of indium arsenide thin films. The spacer layer is formed on the channel layer. The schottky layer is formed on the spacer layer. The cap layer is formed on the schottky layer. | 06-30-2011 |
| 20110186974 | HIGH FREQUENCY FLIP CHIP PACKAGE STRUCTURE OF POLYMER SUBSTRATE - A high frequency flip chip package substrate of a polymer is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost. | 08-04-2011 |
| 20110239932 | Method for reducing defects in epitaxially grown on the group III-nitride materials - The present invention discloses a method to grow group III-nitride materials on a non-native substrate with much reduced threading dislocation (TD) density and smooth surface by using MBE. The first layer is to suppress the formation of screw TD while the second layer is to bend the propagation of edge TD. After that, the migration enhanced epitaxy (MEE) approach is used to smoothen the second layer surface before a main layer of group III-nitride is growth to the thickness required for different applications. All of these steps are performed in the MBE reactor by carefully control over the arrival rate and sequence of group III atoms and nitrogen radicals onto the sample substrate. By using reflective high energy electron diffraction (RHEED), the change of each layer's surface morphology can be monitored during the growth to achieve the high quality group III-nitride materials. | 10-06-2011 |
| 20120025270 | ENHANCEMENT-MODE HIGH-ELECTRON-MOBILITY TRANSISTOR AND THE MANUFACTURING METHOD THEREOF - This invention discloses an enhancement-mode high-electron-mobility transistor and the manufacturing method thereof. The transistor comprises an epitaxial buffer layer on a substrate, a source and drain formed in the buffer layer, a PN-junction stack formed on the buffer layer and located between the source and drain, and a gate formed on the PN-junction stack, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor. | 02-02-2012 |
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| 20090194846 | Fully Cu-metallized III-V group compound semiconductor device with palladium/germanium/copper ohmic contact system - The present invention discloses a fully Cu-metallized III-V group compound semiconductor device, wherein the fully Cu-metallized of a III-V group compound semiconductor device is realized via using an N-type gallium arsenide ohmic contact metal layer formed of a palladium/germanium/copper composite metal layer, a P-type gallium arsenide ohmic contact metal layer formed of a platinum/titanium/platinum/copper composite metal layer, and interconnect metals formed of a titanium/platinum/copper composite metal layer. Thereby, the fabrication cost of III-V group compound semiconductor devices can be greatly reduced, and the performance of III-V group compound semiconductor devices can be greatly promoted. Besides, the heat-dissipation effect can also be increased, and the electric impedance can also be reduced. | 08-06-2009 |
| 20110057196 | GaN HEMT with Nitrogen-Rich Tungsten Nitride Schottky Gate and Method of Forming the Same - A GaN HEMT with Schottky gate is disclosed. The GaN HEMT sequentially has a GaN layer, an AlGaN layer, and a Schottky gate on a substrate, and a source and a drain on two sides of the Schottky gate. The Schottky gate is made by a material of nitrogen-rich tungsten nitride, which has a nitrogen content of about 0.5 molar ratio. | 03-10-2011 |
| 20110146779 | Sub-wavelength structure layer, method for fabricating the same and photoelectric conversion device applying the same - The present invention relates to a method for fabricating a sub-wavelength structure layer, including: forming a metal film on a passivation layer, an n-GaN layer or a transparent conductive oxide layer; performing thermal treatment to form self assembled metal nano particles; using the metal nano particles as a mask to remove a partial area of the passivation layer, the n-GaN layer or the transparent conductive oxide layer to form a sub-wavelength structure of which the cross-sectional area increases along the thickness direction of the passivation layer, the n-GaN layer or the transparent conductive oxide layer; and removing the metal nano particles. In addition, the present invention further provides the obtained sub-wavelength structure layer and a photoelectric conversion device using the same. | 06-23-2011 |
