| Patent application number | Description | Published |
|---|
| 20080200021 | SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK - A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO | 08-21-2008 |
| 20080203491 | RADIATION HARDENED FINFET - The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin. | 08-28-2008 |
| 20080203523 | LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL - Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure and an associated method of forming the semiconductor structure with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals). | 08-28-2008 |
| 20080203524 | LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL - Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed. | 08-28-2008 |
| 20080203540 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 08-28-2008 |
| 20080203544 | SEMICONDUCTOR WAFER STRUCTURE WITH BALANCED REFLECTANCE AND ABSORPTION CHARACTERISTICS FOR RAPID THERMAL ANNEAL UNIFORMITY - Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. | 08-28-2008 |
| 20080217692 | ASYMMETRICALLY STRESSED CMOS FINFET - A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure. | 09-11-2008 |
| 20080217707 | TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT AND RELATED METHODS - A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body. | 09-11-2008 |
| 20080217742 | TAILORED BIPOLAR TRANSISTOR DOPING PROFILE FOR IMPROVED RELIABILITY - Bipolar transistor device structures that improve bipolar device reliability with little or no negative impact on device performance. In one embodiment, the bipolar device has a collector of first conductivity type material formed in a substrate, a base of a second conductivity type material including an extrinsic base layer and an intrinsic base layer, a raised emitter of a first conductivity type semiconductor material formed on the intrinsic base layer, and, a dielectric material layer separating the intrinsic base region and the raised emitter region, and, a thin “shunt” layer of dopant of second conductivity type material added to the region below the emitter dielectric layer. In a second embodiment, a selectively implanted collector (pedestal implant) is added to the vertical bipolar transistor device to enable a reduction in overall subcollector doping level to improve reliability without sacrificing device performance. These solutions add no additional masking steps and only one additional implantation step. | 09-11-2008 |
| 20080265316 | SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate | 10-30-2008 |
| 20080268588 | RECESSED GATE CHANNEL WITH LOW Vt CORNER - A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region. The recessed gate FET device suppresses short channel effects and exhibits improved threshold voltage (Vt) characteristics at corners of the trench bottom. | 10-30-2008 |
| 20080284021 | Method for FEOL and BEOL Wiring - A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension). | 11-20-2008 |
| 20080286905 | Fin-Type Antifuse - A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process. | 11-20-2008 |
| 20080286913 | FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS - Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures. | 11-20-2008 |
| 20080290422 | ASYMMETRIC FIELD EFFECT TRANSISTORS (FETs) - A semiconductor structure. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and (d) a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material; and (e) a gate stack in direct physical contact with the semiconductor channel region. | 11-27-2008 |
| 20080299711 | DUAL WORK-FUNCTION SINGLE GATE STACK - Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes. | 12-04-2008 |
| 20080315264 | STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor. | 12-25-2008 |
| 20090001470 | METHOD FOR FORMING ACUTE-ANGLE SPACER FOR NON-ORTHOGONAL FINFET AND THE RESULTING STRUCTURE - In a method of fabricating a semiconductor finFET transistor for an integrated circuit chip comprising 1) the formation of at least one fin body on the surface of a substrate and 2) the formation of a gate on said fin body in a non-orthogonal orientation relative to the body thereby creating acute angle regions at the crossover of the gate on the body, and 3) the formation of a protective material in the acute angle regions so as to prevent damage to the gate during subsequent fabrication steps. The structure of the finFET transistor comprises such a transistor with protective material in the acute angle regions at the crossover of the gate on the body. | 01-01-2009 |
| 20090020764 | GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region. | 01-22-2009 |
| 20090020806 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 01-22-2009 |
| 20090020819 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 01-22-2009 |
| 20090020830 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 01-22-2009 |
| 20090050975 | Active Silicon Interconnect in Merged Finfet Process - Dummy fins are positioned between source and drain regions of adjacent complementary multi-gate fin-type field effect transistors (MUGFETS) prior to selective silicon growth and silicidation. The dummy fins are parallel to, have the same thickness as, and have a smaller length than the fins within the MUGFETs. Further, the source regions of a first MUGFET, the drain regions of a second MUGFET, and the dummy fins are positioned along a single straight linear path, such that the single straight linear path crosses all of the source regions of the first MUGFET, the drain regions of the second MUGFET, and the dummy fins. Because the dummy fins comprise silicon, the dummy fins enhance the ability to selectively grow silicon within the source/drain connection silicide region. Then, after the source/drain connection silicide region is silicided, a consistently formed and reliable electrical connection is made between the source regions of one transistor and the drain regions of the other transistor to properly connect a CMOS structure. | 02-26-2009 |
| 20090057781 | MUGFET WITH OPTIMIZED FILL STRUCTURES - A semiconductor structure includes active multi-gate fin-type field effect transistor (MUGFET) structures and inactive MUGFET fill structures between the active MUGFET structures. The active MUGFET structures comprise transistors that change conductivity depending upon voltages within gates of the active MUGFET structures. Conversely, the inactive MUGFET fill structures comprise passive devices that do not change conductivity irrespective of voltages within gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures are parallel to the gates of the inactive MUGFET fill structures, and the fins of the active MUGFET structures are the same size as the fins of the inactive MUGFET fill structures. The active MUGFET structures have the same pitch as the gates of the inactive MUGFET fill structures. The gates of the active MUGFET structures comprise active doping agents, but the inactive MUGFET fill structures do not contain the active doping agents. | 03-05-2009 |
| 20090065818 | STRUCTURE FOR IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 03-12-2009 |
| 20090065834 | IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 03-12-2009 |
| 20090078999 | SEMICONDUCTOR DEVICE STRUCTURES WITH FLOATING BODY CHARGE STORAGE AND METHODS FOR FORMING SUCH SEMICONDUCTOR DEVICE STRUCTURES. - Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths. When electrically biased, the floating charge-neutral region at least partially resides in the wider section of the semiconductor body. | 03-26-2009 |
| 20090090983 | DUAL WORK FUNCTION HIGH VOLTAGE DEVICES - A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises a source side positioned toward the source and a drain side positioned toward the drain. The source side comprises a first concentration of conductive doping and the drain side comprises a second concentration of the conductive doping that is less than the first concentration. | 04-09-2009 |
| 20090096026 | METHOD OF FABRICATING HIGH VOLTAGE FULLY DEPLETED SOI TRANSISTOR AND STRUCTURE THEREOF - A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI. | 04-16-2009 |
| 20090096066 | Structure and Method for Device-Specific Fill for Improved Anneal Uniformity - Disclosed is a design structure embodiment of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 04-16-2009 |
| 20090101978 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 04-23-2009 |
| 20090108320 | TUNABLE CAPACITOR - Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions. | 04-30-2009 |
| 20090110023 | BOLOMETRIC ON-CHIP TEMPERATURE SENSOR - Disclosed are embodiments of an improved on-chip temperature sensing circuit, based on bolometry, which provides self calibration of the on-chip temperature sensors for ideality and an associated method of sensing temperature at a specific on-chip location. The circuit comprises a temperature sensor, an identical reference sensor with a thermally coupled heater and a comparator. The comparator is adapted to receive and compare the outputs from both the temperature and reference sensors and to drive the heater with current until the outputs match. Based on the current forced into the heater, the temperature rise of the reference sensor can be calculated, which in this state, is equal to that of the temperature sensor. | 04-30-2009 |
| 20090111225 | CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES - A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation. | 04-30-2009 |
| 20090119626 | DESIGN STRUCTURE INCLUDING TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT - A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. | 05-07-2009 |
| 20090121291 | DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD - Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area. | 05-14-2009 |
| 20090127595 | SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate | 05-21-2009 |
| 20090134463 | SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP - A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer. | 05-28-2009 |
| 20090140328 | Bridged Gate FinFet - In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The gate strap is conformal and, therefore, the top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor. | 06-04-2009 |
| 20090158231 | Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same - A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via. | 06-18-2009 |
| 20090167420 | DESIGN STRUCTURE FOR REGULATING THRESHOLD VOLTAGE IN TRANSISTOR DEVICES - A circuit and a design structure including the circuit embodied in a machine readable medium are disclosed. The circuit is for regulating a desired value of threshold voltage, Vt, for a given FET transistor device. The circuit is coupled to the FET for regulating the desired value of Vt, by providing a device body voltage, and, that additionally enables control of the voltage at the drain of the FET device independent of the applied body bias voltage. The coupled circuit includes an operational amplifier, or, a second MOS transistor, or, a Zener diode. | 07-02-2009 |
| 20090179193 | CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT - Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array. | 07-16-2009 |
| 20090189223 | Complementary Metal Gate Dense Interconnect and Method of Manufacturing - Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal gate to provide an electrical connection between the first metal gate and the second metal gate. | 07-30-2009 |
| 20090197382 | MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES - Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased). | 08-06-2009 |
| 20090206374 | MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR WITH TAILORED DRIVE CURRENT - Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current. | 08-20-2009 |
| 20090206407 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance. | 08-20-2009 |
| 20090209074 | METHOD OF FORMING A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR WITH TAILORED DRIVE CURRENT - Disclosed are embodiments of an improved multi-gated field effect transistor (MUGFET) structure and method of forming the MUGFET structure so that it exhibits a more tailored drive current. Specifically, the MUGFET incorporates multiple semiconductor fins in order to increase effective channel width of the device and, thereby, to increase the drive current of the device. Additionally, the MUGFET incorporates a gate structure having different sections with different physical dimensions relative to the semiconductor fins in order to more finely tune device drive current (i.e., to achieve a specific drive current). Optionally, the MUGFET also incorporates semiconductor fins with differing widths in order to minimize leakage current caused by increases in drive current. | 08-20-2009 |
| 20090236632 | FET HAVING HIGH-K, VT MODIFYING CHANNEL AND GATE EXTENSION DEVOID OF HIGH-K AND/OR VT MODIFYING MATERIAL, AND DESIGN STRUCTURE - A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and a related design structure, are disclosed. In one embodiment, a FET may include a gate having a channel region thereunder including a gate insulator portion of a high dielectric constant (high-k) material and a threshold voltage (Vt) modifying portion (e.g., of SiGe); and a gate extension having a region thereunder devoid of at least one of the high-k material or the Vt modifying portion. | 09-24-2009 |
| 20090239350 | HIGH PERFORMANCE TAPERED VARACTOR - Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode. | 09-24-2009 |
| 20090242985 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed between the gate electrode and the active region of the FET and a method of manufacturing such structure. | 10-01-2009 |
| 20090243000 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 10-01-2009 |
| 20090243029 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 10-01-2009 |
| 20090260669 | METAL-GATE THERMOCOUPLE - A metal gate thermocouple is provided. The thermocouple is configured to measure local temperatures of a device. The thermocouple is a passive device which senses temperature using the thermoelectric principle that when two dissimilar electrically conductive materials are joined, an electrical potential (voltage) is developed between the two materials. The voltage between the materials varies with the temperature of the junction (joint) between the materials. The thermocouple device includes a first conductor comprising a first material formed over a thin oxide layer or a shallow trench isolation (STI) structure and a second conductor comprising a second material formed over the thin oxide layer or the STI structure. The second conductor overlaps with the first conductor to form a thermocouple junction or dimension at least more than an alignment tolerance. The first and second materials are chosen such that the thermocouple junction formed between them exhibits a non-zero Seebeck coefficient. A conductive film formed over the first conductor and the second conductor and a non-conductive void or film is formed over the thermocouple junction. | 10-22-2009 |
| 20090261415 | FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) - Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs. | 10-22-2009 |
| 20090261425 | FINFETs SINGLE-SIDED IMPLANT FORMATION - A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins. | 10-22-2009 |
| 20090267156 | DEVICE STRUCTURES INCLUDING DUAL-DEPTH TRENCH ISOLATION REGIONS AND DESIGN STRUCTURES FOR A STATIC RANDOM ACCESS MEMORY - Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second pluralities of doped regions of a second conductivity type in the first device region. A shallow trench isolation region extends laterally across in the device region to connect the first and second deep trench isolation regions, and is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends from the top surface into the semiconductor layer to a first depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions. | 10-29-2009 |
| 20090269897 | METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL - Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions. | 10-29-2009 |
| 20090298220 | IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A method of fabricating a CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical function. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 12-03-2009 |
| 20090298250 | BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD - A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed. | 12-03-2009 |
| 20090302366 | STRUCTURE AND DESIGN STRUCTURE HAVING ISOLATED BACK GATES FOR FULLY DEPLETED SOI DEVICES - Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure. | 12-10-2009 |
| 20090302374 | Differential Nitride Pullback to Create Differential NFET to PFET Divots for Improved Performance Versus Leakage - Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies. | 12-10-2009 |
| 20090302402 | MUGFET WITH STUB SOURCE AND DRAIN REGIONS - The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the semiconductor fin structure; a gate structure immediately adjacent to the semiconductor fin structure, a dielectric spacer abutting each sidewall of the gate structure wherein the each end of the fin structure extends a dimension that is less than about ¼ a length of the Si-containing fin structure from a sidewall of the dielectric spacer; and a semiconductor region to the each end of the semiconductor fin structure, wherein the semiconductor region to the each end of the semiconductor fin structure is separated from the gate structure by the dielectric spacer. | 12-10-2009 |
| 20090305470 | ISOLATING BACK GATES OF FULLY DEPLETED SOI DEVICES - Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure. | 12-10-2009 |
| 20090309139 | ASYMMETRIC GATE ELECTRODE AND METHOD OF MANUFACTURE - The invention relates to an asymmetric gate electrode and method of manufacturing an asymmetric gate electrode. The method includes: forming a source region and drain region in a substrate; forming a symmetrical gate structure over a channel formed between the source region and the drain region; depositing a material on the substrate and planarizing the material to a top of the symmetrical gate structure; recessing the symmetrical gate structure to below a surface of the material; forming spacers in the recess; protecting one edge of the spacer while etching another edge of the spacer to remove a portion thereof; and recessing the symmetrical gate structure on a side closest to the source region while the another edge of the spacer protects the symmetrical gate structure on a side closest to the drain region to form an asymmetrical gate electrode. | 12-17-2009 |
| 20090319973 | SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION - A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip. | 12-24-2009 |
| 20100006823 | Semiconducting Device Having Graphene Channel - The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure. | 01-14-2010 |
| 20100032796 | Integrated Circuit Structure, Design Structure, and Method Having Improved Isolation and Harmonics - Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation. | 02-11-2010 |
| 20100035403 | Integrated Circuit Structure, Design Structure, and Method Having Improved Isolation and Harmonics - Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation. | 02-11-2010 |
| 20100038694 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE - A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at a first lateral side of the fin and in electrical contact with the conductive region. | 02-18-2010 |
| 20100038720 | STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE - A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The multi-work function metal gate structure comprises a first type of metal with a first work function in a central region and a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function. | 02-18-2010 |
| 20100038724 | Metal-Gate High-K Reference Structure - Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V. Also disclosed are method embodiments for forming the integrated circuit structure. | 02-18-2010 |
| 20100038728 | FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs. | 02-18-2010 |
| 20100039853 | Design Structure, Structure and Method of Using Asymmetric Junction Engineered SRAM Pass Gates - A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; applying a voltage through asymmetric pull-up pFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; and applying a voltage through asymmetrical pass gates which provide low leakage SOI logic. | 02-18-2010 |
| 20100041191 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE - A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor at a first end of the fin; and forming a back-gate at a lateral side of the fin. The back-gate is in electrical contact with the conductive region and is structured and arranged to influence a threshold voltage of the fin. | 02-18-2010 |
| 20100041199 | FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs. | 02-18-2010 |
| 20100041225 | STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE - A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal with a first work function in a central region and forming a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function. | 02-18-2010 |
| 20100044801 | DUAL METAL GATE CORNER - In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated. | 02-25-2010 |
| 20100047972 | SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate. | 02-25-2010 |
| 20100087037 | SEMICONDUCTOR DEVICE STRUCTURES WITH FLOATING BODY CHARGE STORAGE AND METHODS FOR FORMING SUCH SEMICONDUCTOR DEVICE STRUCTURES - Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths. When electrically biased, the floating charge-neutral region at least partially resides in the wider section of the semiconductor body. | 04-08-2010 |
| 20100090320 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 04-15-2010 |
| 20100117125 | SEMICONDUCTOR STRUCTURES INCORPORATING MULTIPLE CRYSTALLOGRAPHIC PLANES AND METHODS FOR FABRICATION THEREOF - A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure. | 05-13-2010 |
| 20100117130 | HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS - A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate. | 05-13-2010 |
| 20100155842 | BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES - A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region. | 06-24-2010 |
| 20100155855 | Band Edge Engineered Vt Offset Device - Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET has a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET. | 06-24-2010 |
| 20100156510 | SOI RADIO FREQUENCY SWITCH FOR REDUCING HIGH FREQUENCY HARMONICS - First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. The first doped semiconductor regions and the second doped semiconductor regions are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6 V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drained through electrical contacts connected to the first and second doped semiconductor regions, thereby reducing of harmonic signals in the semiconductor devices above and enhancing the performance of the semiconductor devices as a radio-frequency (RF) switch. | 06-24-2010 |
| 20100156511 | BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH - A radio frequency (RF) switch located on a semiconductor-on-insulator (SOI) substrate includes at least one electrically biased region in a bottom semiconductor layer. The RF switch receives an RF signal from a power amplifier and transmits the RF signal to an antenna. The electrically biased region may be biased to eliminate or reduce accumulation region, to stabilize a depletion region, and/or to prevent formation of an inversion region in the bottom semiconductor layer, thereby reducing parasitic coupling and harmonic generation due to the RF signal. A voltage divider circuit and a rectifier circuit generate at least one bias voltage of which the magnitude varies with the magnitude of the RF signal. The at least one bias voltage is applied to the at least one electrically biased region to maintain proper biasing of the bottom semiconductor layer to minimize parasitic coupling, signal loss, and harmonic generation. | 06-24-2010 |
| 20100156526 | SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION - A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided. | 06-24-2010 |
| 20100167477 | LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL - Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed. | 07-01-2010 |
| 20100167504 | Methods of Fabricating Nanostructures - A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires. | 07-01-2010 |
| 20100173500 | SEMICONDUCTOR WAFER STRUCTURE WITH BALANCED REFLECTANCE AND ABSORPTION CHARACTERISTICS FOR RAPID THERMAL ANNEAL UNIFORMITY - Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. | 07-08-2010 |
| 20100200840 | GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region. | 08-12-2010 |
| 20100201440 | SOI RADIO FREQUENCY SWITCH WITH REDUCED SIGNAL DISTORTION - A doped semiconductor region having a same conductivity type as a bottom semiconductor layer is formed underneath a buried insulator layer in a bottom semiconductor layer of a semiconductor-on-insulator (SOI) substrate. At least one conductive via structure is formed, which extends from a interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to the doped semiconductor region. The shallow trench isolation structure laterally abuts at least one field effect transistor that functions as a radio frequency (RF) switch. During operation, the doped semiconductor region is biased at a voltage that keeps an induced charge layer within the bottom semiconductor layer in a depletion mode and avoids an accumulation mode. Elimination of electrical charges in an accumulation mode during half of each frequency cycle reduces harmonic generation and signal distortion in the RF switch. | 08-12-2010 |
| 20100203689 | finFET TRANSISTOR AND CIRCUIT - A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin. | 08-12-2010 |
| 20100211923 | Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same - A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via. | 08-19-2010 |
| 20100230779 | TRENCH GENERATED DEVICE STRUCTURES AND DESIGN STRUCTURES FOR RADIOFREQUENCY AND BICMOS INTEGRATED CIRCUITS - Trench-generated device structures fabricated using a semiconductor-on-insulator (SOI) wafer, design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, as well as methods for fabricating trench-generated device structures. The device structure includes a trench extending through the semiconductor and insulator layers of the SOI wafer and into the underlying semiconductor substrate, and a first doped region in the semiconductor substrate. The doped region, which extends about the trench, has a second conductivity type opposite to the first conductivity type. The device structure further includes a first contact extending from the top surface through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region, and a second contact extending from the top surface through the semiconductor and insulator layers to the doped region in the semiconductor substrate. | 09-16-2010 |
| 20100232212 | SPLIT-GATE DRAM WITH LATERAL CONTROL-GATE MUGFET - A semiconductor structure of an array of dynamic random access memory cells. The structure includes: a first fin of a first split-gate fin-type field effect transistor (FinFET) device on a substrate; a second fin of a second split-gate fin-type field effect transistor (FinFET) device on the substrate; and a back-gate associated with the first fin and the second fin. The back-gate influences a threshold voltage of the first fin and a threshold voltage of the second fin. | 09-16-2010 |
| 20100233873 | METHOD OF FORMING A SEMICONDUCTOR DEVICE USING A SACRIFICIAL UNIFORM VERTICAL THICKNESS SPACER STRUCTURE - Disclosed is a method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method forms such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate structure. The use of an epitaxial growth process, as opposed to a deposition and etch process, ensures that the resulting spacers will have a uniform vertical thickness. Then, any process steps (e.g., implant and/or etch process steps) requiring the use of the gate sidewall spacers (e.g., as a mask or shield) are performed. Precise implant and/or etch profiles can be achieved, during these process steps, as a function of the uniformity of the gate sidewall spacers. Once such process steps are completed, the sidewall spacers are selectively removed. Optionally, before removing the sidewall spacers, they can be oxidized in order to enhance the selective removal process. | 09-16-2010 |
| 20100244934 | SOI RADIO FREQUENCY SWITCH WITH ENHANCED ELECTRICAL ISOLATION - At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced. | 09-30-2010 |
| 20100276753 | Threshold Voltage Adjustment Through Gate Dielectric Stack Modification - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 11-04-2010 |
| 20100295025 | CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT - Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array. | 11-25-2010 |
| 20100301419 | INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS ANDAN UNDERLYING FLOATING WELL SECTION - Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions used for intra-well isolation effectively create some floating well sections, which must each be connected to a supply voltage (e.g., Vdd) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact to a junction between the diffusion regions of adjacent devices and an underlying floating well section. This shared contact eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section. | 12-02-2010 |
| 20100314688 | DIFFERENTIAL NITRIDE PULLBACK TO CREATE DIFFERENTIAL NFET TO PFET DIVOTS FOR IMPROVED PERFORMANCE VERSUS LEAKAGE - Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies. | 12-16-2010 |
| 20100323462 | PROCESS ENVIRONMENT VARIATION EVALUATION - Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined. | 12-23-2010 |
| 20100327360 | FET With Replacement Gate Structure and Method of Fabricating the Same - A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material. | 12-30-2010 |
| 20110006359 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material. | 01-13-2011 |
| 20110029274 | SELF HEATING MONITOR FOR SiGe AND SOI CMOS DEVICES - A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents. | 02-03-2011 |
| 20110042748 | MULTI-GATE NON-PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE USING A DOPANT IMPLANT PROCESS TO TUNE DEVICE DRIVE CURRENT - Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, a dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure. | 02-24-2011 |
| 20110049724 | BEOL INTERCONNECT STRUCTURES AND RELATED FABRICATION METHODS - Methods for forming voids in BEOL interconnect structures and BEOL interconnect structures. The methods include forming a temporary feature on a top surface of a first dielectric layer and depositing a second dielectric layer on the top surface of the first dielectric layer. The temporary feature is removed from the second dielectric layer to define a void in the second dielectric layer that is laterally adjacent to a conductive feature in the second dielectric layer. The void operates to reduce the effective dielectric constant of the second dielectric layer, which reduces parasitic capacitance between the conductive feature and other conductors in the BEOL interconnect structure. | 03-03-2011 |
| 20110057258 | DUAL STRESS DEVICE AND METHOD - A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. | 03-10-2011 |
| 20110062555 | SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO - A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region. | 03-17-2011 |
| 20110068398 | TRENCH-GENERATED TRANSISTOR STRUCTURES, FABRICATION METHODS, DEVICE STRUCTURES, AND DESIGN STRUCTURES - Trench-generated transistor structures, methods for fabricating transistors using a trench defined in a semiconductor-on-insulator (SOI) wafer, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of the SOI wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer. Alternatively, the gate electrode may be defined as a conventional gate stack on a shallow trench isolation region in the semiconductor layer or as a conventional gate stack in one of the BEOL interconnect levels. | 03-24-2011 |
| 20110068399 | INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE - Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body. | 03-24-2011 |
| 20110068414 | INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIN-TYPE FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE - Disclosed is an integrated circuit device having stacked fin-type field effect transistors (FINFETs) with integrated voltage equalization and a method. A multi-layer fin includes a semiconductor layer, an insulator layer above the semiconductor layer and a high resistance conductor layer above the insulator layer. For each FINFET, a gate is positioned on the sidewalls and top surface of the fin and source/drain regions are within the semiconductor layer on both sides of the gate. Thus, the portion of the semiconductor layer between any two gates contains a source/drain region of one FINFET abutting a source/drain region of another. Conductive straps are positioned on opposing ends of the fin and also between adjacent gates in order to electrically connect the semiconductor layer to the conductor layer. Contacts electrically connect the conductive straps at the opposing ends of the fin to positive and negative supply voltages, respectively. | 03-24-2011 |
| 20110079828 | METAL GATE FET HAVING REDUCED THRESHOLD VOLTAGE ROLL-OFF - A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material. | 04-07-2011 |
| 20110101449 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 05-05-2011 |
| 20110108927 | DAMASCENE GATE HAVING PROTECTED SHORTING REGIONS - The present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate with protected shorting regions, the method comprising: forming a damascene gate having: a gate dielectric atop a substrate; a gate conductor atop the gate dielectric; a conductive liner laterally adjacent the gate conductor; a spacer between the conductive liner and the substrate; and a first dielectric atop the gate conductor; removing a portion of the conductive liner; and depositing a second dielectric atop a remaining portion of the conductive liner, such that the second dielectric is laterally adjacent both the first dielectric and the gate. | 05-12-2011 |
| 20110121369 | INTEGRATED CIRCUIT INCLUDING FINFET RF SWITCH ANGLED RELATIVE TO PLANAR MOSFET AND RELATED DESIGN STRUCTURE - An integrated circuit (IC) includes a fin field effect transistor (FinFET) radio frequency (RF) switch; and a planar complementary metal-oxide semiconductor field effect transistor (MOSFET). The planar MOSFET has a channel on a <100> wafer plane and the FinFET RF switch has a channel on a <100> fin plane. The FinFET RF switch and the planar MOSFET can be oriented at approximately 45° with respect to one another. | 05-26-2011 |
| 20110121862 | CIRCUIT WITH STACKED STRUCTURE AND USE THEREOF - An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET. | 05-26-2011 |
| 20110133310 | INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT - Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s). | 06-09-2011 |
