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| 20100311927 | PROCESS TO MAKE LONG CHAIN BRANCHED (LCB), BLOCK, OR INTERCONNECTED COPOLYMERS OF ETHYLENE - A process is taught, comprising polymerizing ethylene in the presence of a catalyst to form a crystalline ethylene-based polymer having a crystallinity of at least 50% as determined by DSC Crystallinity in a first reactor or a first part of a multi-part reactor and reacting the crystalline ethylene-based polymer with additional ethylene in the presence of a free-radical initiator to form an ethylenic polymer in at least one other reactor or a later part of a multi-part reactor. | 12-09-2010 |
| 20110130533 | PROCESS TO MAKE LONG CHAIN BRANCHED (LCB), BLOCK, OR INTERCONNECTED COPOLYMERS OF ETHYLENE - A process is taught, comprising polymerizing ethylene in the presence of a catalyst to form a crystalline ethylene-based polymer having a crystallinity of at least 50% as determined by DSC Crystallinity in a first reactor or a first part of a multi-part reactor and reacting the crystalline ethylene-based polymer with additional ethylene in the presence of a free-radical initiator to form an ethylenic polymer in at least one other reactor or a later part of a multi-part reactor. | 06-02-2011 |
| 20110178253 | HIGH PRESSURE LOW DENSITY POLYETHYLENE RESINS WITH IMPROVED OPTICAL PROPERTIES PRODUCED THROUGH USE OF HIGHLY ACTIVE CHAIN TRANSFER AGENTS - Disclosed is an ethylene-based polymer with a density from about 0.90 to about 0.94 in grams per cubic centimeter, with a molecular weight distribution (M | 07-21-2011 |
| 20110196105 | NOVEL HIGH PRESSURE, LOW DENSITY POLYETHYLENE RESINS PRODUCED THROUGH THE USE OF HIGHLY ACTIVE CHAIN TRANSFER AGENTS - In one aspect the invention is a reaction product comprising ethylene and at least one cyclic phosphine wherein the reaction product has a non-extractable phosphorous concentration of at least 10 parts per million by weight, and preferably a maximum of at least about 10000 ppm by weight, preferably wherein the reaction product has a density from about 0.90 to about 0.94 in grams per cubic centimeter, a molecular weight distribution (M | 08-11-2011 |
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| 20080256336 | MICROPROCESSOR WITH PRIVATE MICROCODE RAM - A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR. | 10-16-2008 |
| 20090204800 | MICROPROCESSOR WITH MICROARCHITECTURE FOR EFFICIENTLY EXECUTING READ/MODIFY/WRITE MEMORY OPERAND INSTRUCTIONS - The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location. | 08-13-2009 |
| 20100011188 | MICROPROCESSOR THAT PERFORMS SPECULATIVE TABLEWALKS - A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page. | 01-14-2010 |
| 20100011198 | MICROPROCESSOR WITH MULTIPLE OPERATING MODES DYNAMICALLY CONFIGURABLE BY A DEVICE DRIVER BASED ON CURRENTLY RUNNING APPLICATIONS - A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss. | 01-14-2010 |
| 20100049952 | MICROPROCESSOR THAT PERFORMS STORE FORWARDING BASED ON COMPARISON OF HASHED ADDRESS BITS - An apparatus for decreasing the likelihood of incorrectly forwarding store data includes a hash generator, which hashes J address bits to K hashed bits. The J address bits are a memory address specified by a load/store instruction, where K is an integer greater than zero and J is an integer greater than K. The apparatus also includes a comparator, which outputs a first value if L address bits specified by the load instruction match L address bits specified by the store instruction and K hashed bits of the load instruction match corresponding K hashed bits of the store instruction, and otherwise to output a second value, where L is greater than zero. The apparatus also includes forwarding logic, which forwards data from the store instruction to the load instruction if the comparator outputs the first value and foregoes forwarding the data when the comparator outputs the second value. | 02-25-2010 |
| 20100064107 | MICROPROCESSOR CACHE LINE EVICT ARRAY - An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy includes an eviction engine and an array of storage elements. The eviction engine is configured to move the cache line from the lower-level memory to the higher-level memory. The array of storage elements are coupled to the eviction engine. Each storage element is configured to store an indication for a corresponding cache line stored in the lower-level memory. The indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory. | 03-11-2010 |
