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Easwaran
Arunkumar Easwaran, Media, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20110118459 | HIGH PERFORMANCE LUMINESCENT COMPOUNDS - Embodiments relate to the field of chemistry and biochemistry, and, more specifically, to novel near-infrared dyes that are photostable and resistant to quenching. The dyes belong to a novel family of squaraine rotaxanes, and they are particularly well-suited for use in biological applications. Also disclosed are methods of synthesizing the dyes and methods of using the dyes. | 05-19-2011 |
Hariharan Easwaran, Baltimore, MD US
| Patent application number | Description | Published |
|---|---|---|
| 20110165565 | COMPOSITIONS AND METHODS FOR POLYNUCLEOTIDE EXTRACTION AND METHYLATION DETECTION - The present invention features methods and compositions for methylation detection, as well as a novel method for polynucleotide extraction and sodium bisulfite treatment. | 07-07-2011 |
Prakash Easwaran, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090278516 | TRANSIENT RECOVERY CIRCUIT FOR SWITCHING DEVICES - A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage. | 11-12-2009 |
| 20090295609 | SYSTEM AND METHOD FOR REDUCING POWER DISSIPATION IN AN ANALOG TO DIGITAL CONVERTER - A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs. | 12-03-2009 |
| 20100026267 | SINGLE INDUCTOR MULTIPLE OUTPUT SWITCHING DEVICES - Single inductor multiple output (SIMO) switching devices with efficient regulating circuits. The SIMO switching device includes a plurality of time division multiplexing (TDM) switches for switching current through an inductor of the SIMO switching device. The plurality of TDM switches produces a plurality of outputs. The SIMO switching device further includes an error calculation circuit operatively coupled to the plurality of outputs for determining a calculated error from the plurality of outputs; a time slot generation circuit for controlling the plurality of TDM switches according to the calculated error; and a pulse width modulation (PWM) control circuit operatively coupled to the time slot generation circuit for controlling a plurality of PWM switches of a switching stage of the SIMO switching device in a continuous conduction mode (CCM) of operation. The PWM switches are controlled according to the time slots generated by the time slot generation circuit. | 02-04-2010 |
| 20100164606 | DC BIASING CIRCUIT FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR - A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes. | 07-01-2010 |
| 20100164611 | LEAKAGE INDEPENDENT VRY LOW BANDWIDTH CURRENT FILTER - A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit. | 07-01-2010 |
| 20100283439 | EFFICIENT SWITCH CASCODE ARCHITECTURE FOR SWITCHING DEVICES - Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions. | 11-11-2010 |
Shriram K. Easwaran, Randolph, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20120028636 | APPARATUS FOR MULTI-CELL SUPPORT IN A NETWORK - An apparatus for providing multi-cell support in a telecommunications network is described. The apparatus includes a modem board and a multi-core processor having a plurality of processor cores attached to the modem board. A single partition is defined with all of the processor cores included in it. The single partition is used to execute all control plane functions and all data plane functions. Typically, the multi-core processor is configured to include a core abstraction layer that hides any core specific details from application software running on the processor cores in the single partition and to serve at least three cells in the telecommunications network, each cell having a corresponding uplink scheduler and a corresponding downlink scheduler. In this configuration there is no need to use a hypervisor, since there is only one OS instance running (a potential cost saving). | 02-02-2012 |
Sri N. Easwaran, Freising DE
| Patent application number | Description | Published |
|---|---|---|
| 20090206811 | CURRENT LIMITED VOLTAGE SOURCE WITH WIDE INPUT CURRENT RANGE - An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current. Further, a current limiting stage is coupled to the output node for limiting the selected current to a predefined magnitude. | 08-20-2009 |
| 20100039144 | CURRENT DRIVER CIRCUIT - An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements. | 02-18-2010 |
Sri Navaneethakrishnan Easwaran, Zurich CH
| Patent application number | Description | Published |
|---|---|---|
| 20080297214 | Low Lock Time Delay Locked Loops Using Time Cycle Suppressor - A delay locked loop (DLL) architecture includes a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit. | 12-04-2008 |
Sri Navaneethakrishnan Easwaran, Freising DE
| Patent application number | Description | Published |
|---|---|---|
| 20090189647 | BIAS CURRENT GENERATOR FOR MULTIPLIE SUPPLY VOLTAGE CIRCUIT - An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current. | 07-30-2009 |
| 20110216468 | ELECTRONIC DEVICE FOR CONTROLLING A CURRENT - An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground. | 09-08-2011 |