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Dyi-Chung
Dyi-Chung Hu, Chutung Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090321915 | System-in-package and manufacturing method of the same - The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via. | 12-31-2009 |
| 20100007017 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD FOR THE SAME - The present invention discloses an inter-connecting structure for a semiconductor package and a method for the same. The inter-connecting structure for the semiconductor package comprises a substrate formed to support a die thereon; core paste formed on the substrate and adjacent to the die; and a stiffener formed in an upper portion of the core paste, wherein the hardness of the stiffener is larger than the hardness of the core paste. | 01-14-2010 |
| 20100109156 | BACK SIDE PROTECTIVE STRUCTURE FOR A SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; a conductive layer formed upon the back surface of the die; and a protection substrate formed on the conductive layer. An adhesive layer is formed between the conductive layer and the protective layer, if necessary. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming a conductive layer upon the back surface of the die; forming protection substrates on the conductive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation by exerting external force on the substrate. An adhesive layer is formed between the conductive layer and the protective layer, if necessary. | 05-06-2010 |
Dyi-Chung Hu, Chutung TW
| Patent application number | Description | Published |
|---|---|---|
| 20080199391 | Method for circuits inspection and the method of the same - A method for circuit inspection comprises steps of providing a substrate having a conductive line; and forming a metal layer on at least the conductive layer to increase a contrast between the conductive layer and adjacent area for the circuit inspection. The method further comprising removing the metal layer. The metal layer is removed by a mixture of nitric acid, hydrogen peroxide and fluoride boric acid. The metal includes Silver, Nickel or Tin. The deposit metal can be removed by inter diffusion and form intermetallic compounds (for example Cu | 08-21-2008 |
| 20090184425 | Conductive line structure and the method of forming the same - The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut generated by etching. The structure further comprises an underlying layer under the conductive line. The underlying layer includes Ni, Cu or Pt. The conductive line includes gold or copper. The at least one patterned conductive layer includes at least Ti/Cu. The protection layer includes electro-less plating Sn, Au, Ag or Ni. | 07-23-2009 |
Dyi-Chung Hu, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080237834 | CHIP PACKAGING STRUCTURE AND CHIP PACKAGING PROCESS - A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost. | 10-02-2008 |