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Dutt, CA

Birendra Dutt, Westchester, CA US

Patent application numberDescriptionPublished
20090068570PHOTOLITHOGRAPHIC MASK EXHIBITING ENHANCED LIGHT TRANSMISSION DUE TO UTILIZING SUB-WAVELENGTH APERTURE ARRAYS FOR IMAGING PATTERNS IN NANO-LITHOGRAPHY - A nanophotolithography mask includes a layer of an electrically conductive optically opaque material deposited on a mask substrate in which regular arrays of sub-wavelength apertures are formed. The plasmonic excitation in the layer perforated with the sub-wavelength apertures arrays under the light incident on the mask produces high resolution far-field radiation patterns of sufficient intensity to expose a photoresist on a wafer when propagated to the same. The fill-factor of the mask, i.e., the ratio of the total apertures area to the total mask area, may lead to a significant increase in mask manufacturing throughput by FIB or electron beam “writing”. The mask demonstrates the defect resiliency and ability to imprint coherent clear features of nano dimensions and shapes on the wafers for integrated circuits design.03-12-2009
20090201475STEPPER SYSTEM FOR ULTRA-HIGH RESOLUTION PHOTOLITHOGRAPHY USING PHOTOLITHOGRAPHIC MASK EXHIBITING ENHANCED LIGHT TRANSMISSION DUE TO UTILIZING SUB-WAVELENGTH APERTURE ARRAYS - A stepper system for ultra-high resolution nano-lithography employs a photolithographic mask which includes a layer of an electrically conductive optically opaque material in which periodic arrays of sub-wavelength apertures are formed. The plasmonic excitation in the photolithographic mask exposed to the light of the wavelength in the range of 197 nm-248 nm, produces high resolution far-field radiation patterns of sufficient intensity to expose a photoresist on a wafer. The stepper system demonstrates the resiliency to the mask defects and ability to imprint coherent clear features of nano dimensions (45 nm-500 nm) and various shapes on the wafers for integrated circuits design. The stepper system may be adjusted to image the plane of the highest plasmonic field exiting the mask.08-13-2009

Dinesh Dutt, Sunnyvale, CA US

Patent application numberDescriptionPublished
20090006746Online Restriping Technique for Distributed Network Based Virtualization - A technique is provided for implementing online restriping of a volume in a storage area network. A first instance of the volume is instantiated at a first port of the fibre channel fabric for enabling I/O operations to be performed at the volume. While restriping operations are being performed at the volume, the first port is able to concurrently perform I/O operations at the volume.01-01-2009
20090052326BACKWARD CONGESTION NOTIFICATION - In one embodiment, an apparatus comprises a network interface system having at least one input port configured for receiving frames and a logic system comprising at least one logic device. The logic system may be configured to perform the following functions: determining a source address and a destination address of a frame received at an ingress port; calculating a flow hash based at least upon the source address and the destination address; forming a congestion management (“CM”) tag that includes the flow hash; inserting the CM tag in the frame; and forwarding the frame to the destination address.02-26-2009
20090259816Techniques for Improving Mirroring Operations Implemented In Storage Area Networks and Network Based Virtualization - A technique is provided for implementing online mirroring of a volume in a storage area network. A first instance of the volume is instantiated at a first port of the fibre channel fabric for enabling I/O operations to be performed at the volume. One or more mirroring procedures may be performed at the volume. In at least one implementation, the first port is able to perform first I/O operations at the volume concurrently while the mirroring procedures are being performed at the first volume. In one implementation, the mirroring procedures may be implemented at a fabric switch of the storage area network. Additionally, in at least one implementation, multiple hosts may be provided with concurrent access to the volume during the mirroring operations without serializing the access to the volume.10-15-2009
20090259817Mirror Consistency Checking Techniques For Storage Area Networks And Network Based Virtualization - A technique is provided for facilitating information management in a storage area network. The storage area network may utilize a fibre channel fabric which includes a plurality of ports. The storage area network may also comprise a first volume which includes a first mirror copy and a second mirror copy. The storage area network may further comprise a mirror consistency data structure adapted to store mirror consistency information. A mirror consistency check procedure is performed to determine whether data of the first mirror copy is consistent with data of the second mirror copy. According to one implementation, the mirror consistency check procedure may be implemented using the consistency information stored at the mirror consistency data structure.10-15-2009
20110222402ETHERNET EXTENSION FOR THE DATA CENTER - The present invention provides methods and devices for implementing a Low Latency Ethernet (“LLE”) solution, also referred to herein as a Data Center Ethernet (“DCE”) solution, which simplifies the connectivity of data centers and provides a high bandwidth, low latency network for carrying Ethernet and storage traffic. Some aspects of the invention involve transforming FC frames into a format suitable for transport on an Ethernet. Some preferred implementations of the invention implement multiple virtual lanes (“VLs”) in a single physical connection of a data center or similar network. Some VLs are “drop” VLs, with Ethernet-like behavior, and others are “no-drop” lanes with FC-like behavior. Some preferred implementations of the invention provide guaranteed bandwidth based on credits and VL. Active buffer management allows for both high reliability and low latency while using small frame buffers. Preferably, the rules for active buffer management are different for drop and no drop VLs.09-15-2011
20110243136Forwarding multi-destination packets in a network with virtual port channels - In one embodiment, a method includes receiving a multi-destination packet at a switch in communication with a plurality of servers through a network device, identifying a port receiving the multi-destination packet at the switch or a forwarding topology for the multi-destination packet, selecting a bit value based on the identified port or forwarding topology, inserting the bit value into a field in a virtual network tag in the multi-destination packet, and forwarding the multi-destination packet with the virtual network tag to the network device. The network device is configured to forward the multi-destination packet to one or more of the servers based on the bit value in the multi-destination packet. An apparatus for forwarding multi-destination packets is also disclosed.10-06-2011

Patent applications by Dinesh Dutt, Sunnyvale, CA US

Dinesh G. Dutt, Sunnyvale, CA US

Patent application numberDescriptionPublished
20090019142Fibre channel intelligent target management system - In one embodiment, a network device receives a port login directed to a target from a first host. The network device determines whether at least one other host is currently logged in to the target. The network device may then send a port login to the target corresponding to whether at least one other host is currently logged in to the target.01-15-2009
20090162058FIBRE CHANNEL FABRIC AND SWITCHES WITH FLEXIBLE PREFIX ADDRESSING - A way to assign flexible prefixes to Switches in Fibre Channel Fabrics while using the currently defined FC_ID address space. This allows end devices in different Fibre Channel Fabrics to communicate with one another, without requiring modifications to existing end devices, nor to perform Network Address Translation between Fabrics. The existing address space for each Switch includes a dynamically configurable number of host bits sufficient to address all the end devices coupled to the Switch and the Switch itself. The remaining bits, called the Switch prefix, are used to identify the Switch in the switching Fabric. In an alternative embodiment, the Switch prefix bits may be further configured into a first sub-set of bits used to identify a specific Fabric (Fabric prefix) and a second sub-set of bits used to identify the Switch in the Fabric (Switch_ID). The flexible addressing scheme enables end devices in different Fabrics to communicate with one another without expanding the Fibre Channel address space or the need to perform Network Address Translations.06-25-2009
20090172816DETECTING ROOTKITS OVER A STORAGE AREA NETWORK - Embodiments of the invention improve the detection of malicious software applications, such as a rootkit, on hosts configured to access storage volumes over a storage area network (SAN). A rootkit detection program running on a switch may be configured to detect rootkits present on the storage volumes of the SAN. Because the switch may mount and access storage volumes independently from the (possibly comprised) hosts, the rootkit is not able to conceal itself from the rootkit detection program running on the switch.07-02-2009
20090287892EPOCH-BASED MUD LOGGING - In one embodiment, a MUD logger receives a notification from another MUD logger maintaining another MUD log for a volume, the notification indicating one or more modifications to be made to a MUD log maintained by the MUD logger receiving the notification, wherein the MUD log includes information for one or more epochs, wherein the information for each of the epochs indicates a set of one or more regions of the volume that have been modified during the corresponding epoch. The MUD logger updates the MUD log associated with the volume, wherein updating the MUD log is performed in response to the notification.11-19-2009
20100008375LABEL SWITCHING IN FIBRE CHANNEL NETWORKS - Methods and apparatus are provided for label switched routing in fibre channel networks. Techniques are provided for implementing label switching based on particular characteristics of fibre channel networks. By using label switching, mechanisms such as traffic engineering, security, and tunneling through networks that do not support fibre channel frames can be implemented.01-14-2010
20110267947Load Balancing Over DCE Multipath ECMP Links for HPC and FCoE - Methods and apparatus for generating different hash values in an effort to achieve better load balancing among various paths in a data center environment, such as Data Center Ethernet (DCE) with Layer 2 Multipathing (L2MP), supporting equal-cost multipath (ECMP) routing are provided. In this manner, the data center environment may attain better network utilization for high-performance computing (HPC), storage area network (SAN), and/or local area network (LAN) traffic.11-03-2011
20120106339Probing Specific Customer Flow in Layer-2 Multipath Networks - Techniques are provided to enable a switch in a layer-2 multipath network to determine connectivity of a path to a destination switch. At a source switch, user flow parameters are determined for user flow packets to be transported in the layer-2 multipath network to a destination switch. The sourced switch determines a number of hops from it to the destination switch based on the user flow parameters. Timestamping is activated for time-to-live expiry packets received at the source switch and for time-to-live expiry packets received at the destination switch. One or more probe packets having user flow parameters matching the user flow parameters of user flow packets are generated so that the probe packets use the same path taken by the user flow packets between the source switch and the destination switch. In addition, a time-to-live value corresponding to the number of hops from the source switch to the destination switch is included in a hop count field of the one or more probe packets. The time-to-live value distinguishes the one or more probe packets from user flow packets. The one or more probe packets are sent in the layer-2 multipath network from the source switch to the destination switch. Connectivity between the source switch and the destination switch is determined based on the one or more probe packets.05-03-2012

Patent applications by Dinesh G. Dutt, Sunnyvale, CA US

Dinesh G. Dutt, San Jose, CA US

Patent application numberDescriptionPublished
20090141657FIBRE CHANNEL SWITCH THAT ENABLES END DEVICES IN DIFFERENT FABRICS TO COMMUNICATE WITH ONE ANOTHER WHILE RETAINING THEIR UNIQUE FIBRE CHANNEL DOMAIN_IDs - A Fibre Channel Switch which enables end devices in different Fabrics to communicate with one another while retaining their unique Fibre Channel Domain_IDs. The Switch is coupled to a first fabric having a first set of end devices and a second fabric having a second set of end devices. The Switch is configured to enable communication by the first set of end devices associated with the first fabric with the second set of end devices associated with the second set of end devices using the unique Domain_IDs of each of the first set and the second set of end devices. In one embodiment of the invention, the first and second fabrics are first and second Virtual Storage Array Networks (VSANs) respectively. In an alternative embodiment, the first fabric and the second fabric are separate physical fabrics.06-04-2009
20110090816FIBRE CHANNEL SWITCH THAT ENABLES END DEVICES IN DIFFERENT FABRICS TO COMMUNICATE WITH ONE ANOTHER WHILE RETAINING THEIR UNIQUE FIBRE CHANNEL DOMAIN_IDs - A Fibre Channel Switch which enables end devices in different Fabrics to communicate with one another while retaining their unique Fibre Channel Domain_IDs. The Switch is coupled to a first fabric having a first set of end devices and a second fabric having a second set of end devices. The Switch is configured to enable communication by the first set of end devices associated with the first fabric with the second set of end devices associated with the second set of end devices using the unique Domain_IDs of each of the first set and the second set of end devices. In one embodiment of the invention, the first and second fabrics are first and second Virtual Storage Array Networks (VSANs) respectively. In an alternative embodiment, the first fabric and the second fabric are separate physical fabrics.04-21-2011

Dinesh Ganapathy Dutt, Sunnyvale, CA US

Patent application numberDescriptionPublished
20090103566SWITCH PORT ANALYZERS - Methods and devices are provided for non-disruptive monitoring of network traffic through one or more ports of a Fibre Channel network device. Preferred embodiments of the invention are used in conjunction with the switched port analyzer (“SPAN”) and/or remote SPAN (“RSPAN”) features. SPAN mode operation allows traffic through any Fibre Channel interface of a network device to be replicated and delivered to a single port on the same network device. Ingress SPAN allows the monitoring of some or all packets that ingress a specified port or ports. Egress SPAN allows the monitoring of some or all packets that egress a specified port or ports. RSPAN allows the delivery of the replicated traffic to a port on a remote network device. Filtering may be applied, for example, to SPAN packets having selected virtual storage area network numbers.04-23-2009

Gyan Dutt, Garden Grove, CA US

Patent application numberDescriptionPublished
20100007018PROCESS FOR COATING A BUMPED SEMICONDUCTOR WAFER - A process is described that enables the active side of a bumped wafer to be coated with a front side protection (FSP) material or wafer level underfill (WLUF) without contaminating the solder bumps with the coating material and/or filler. In this process a repellent material is applied to a top portion of the solder bumps on the active side of the wafer, the front side of the wafer is then coated with the coating material, the coating material is hardened, and optionally the repellent material is removed from the solder bumps.01-14-2010

Nikil Dutt, Irvine, CA US

Patent application numberDescriptionPublished
20120105099Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design - Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.05-03-2012