Patent application number | Description | Published |
20080254580 | Realization of Self-Positioned Contacts by Epitaxy - Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface. | 10-16-2008 |
20090023275 | METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS - A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer. | 01-22-2009 |
20090032874 | METHOD FOR INTEGRATING SILICON-ON-NOTHING DEVICES WITH STANDARD CMOS DEVICES - A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit. | 02-05-2009 |
20110140220 | MICROELECTRONIC DEVICE, IN PARTICULAR BACK SIDE ILLUMINATED IMAGE SENSOR, AND PRODUCTION PROCESS - A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer. | 06-16-2011 |
20120252174 | PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS - A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor. | 10-04-2012 |
20130072032 | METHOD FOR DEPOSITING A SILICON OXIDE LAYER OF SAME THICKNESS ON SILICON AND ON SILICON-GERMANIUM - A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate. | 03-21-2013 |
20130075870 | METHOD FOR PROTECTION OF A LAYER OF A VERTICAL STACK AND CORRESPONDING DEVICE - A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed. | 03-28-2013 |
20130095636 | PROCESS FOR PRODUCING AT LEAST ONE DEEP TRENCH ISOLATION - A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation. | 04-18-2013 |
20140363953 | METHOD FOR FORMING COMPONENTS ON A SILICON-GERMANIUM LAYER - A method for manufacturing components on an SOI layer coated with a silicon-germanium layer formed by epitaxial deposition, wherein the heat balance of the anneals performed after the epitaxial deposition is such that the germanium concentration remains higher in the silicon-germanium layer than in the SOI layer. | 12-11-2014 |
Patent application number | Description | Published |
20120301465 | COMPOSITIONS AND METHODS TO IMMUNIZE AGAINST HEPATITIS C VIRUS - Compositions comprising viral antigens and antigenic peptides corresponding to or derived from Hepatitis C virus (HCV) proteins or fragments thereof, fused to heavy and/or light chain of antibodies, or fragments thereof specific for dendritic cells (DCs) are described herein. Included herein are immunostimulatory compositions (HCV vaccines, HCV antigen presenting dendritic cells, etc.) and methods for increasing effectiveness of HCV antigen presentation by an antigen presenting cell, for a treatment, a prophylaxis or a combination thereof against hepatitis C in a human subject, and methods of providing immunostimulation by activation of one or more dendritic cells, methods to treat or prevent hepatitis C. | 11-29-2012 |
20140199763 | COMPOSITIONS AND METHODS TO IMMUNIZE AGAINST HEPATITIS C VIRUS - Compositions comprising viral antigens and antigenic peptides corresponding to or derived from Hepatitis C virus (HCV) proteins or fragments thereof, fused to heavy and/or light chain of antibodies, or fragments thereof specific for dendritic cells (DCs) are described herein. Included herein are immunostimulatory compositions (HCV vaccines, HCV antigen presenting dendritic cells, etc.) and methods for increasing effectiveness of HCV antigen presentation by an antigen presenting cell, for a treatment, a prophylaxis or a combination thereof against hepatitis C in a human subject, and methods of providing immunostimulation by activation of one or more dendritic cells, methods to treat or prevent hepatitis C. | 07-17-2014 |