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Durocher, US

Kevin Durocher, Waterford, NY US

Patent application numberDescriptionPublished
20090243081SYSTEM AND METHOD OF FORMING A WAFER SCALE PACKAGE - A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.10-01-2009
20100078797SYSTEM AND METHOD FOR PRE-PATTERNED EMBEDDED CHIP BUILD-UP - A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.04-01-2010

Patent applications by Kevin Durocher, Waterford, NY US

Kevin M. Durocher, Waterford, NY US

Patent application numberDescriptionPublished
20100132994APPARATUS AND METHOD FOR REDUCING PITCH IN AN INTEGRATED CIRCUIT - An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.06-03-2010
20100133683SYSTEM AND APPARATUS FOR VENTING ELECTRONIC PACKAGES AND METHOD OF MAKING SAME - An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.06-03-2010
20100133705APPARATUS AND METHOD FOR REDUCING PITCH IN AN INTEGRATED CIRCUIT - An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.06-03-2010
20100224992SYSTEM AND METHOD FOR STACKED DIE EMBEDDED CHIP BUILD-UP - An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.09-09-2010

Lisa L. Durocher, Warren, NJ US

Patent application numberDescriptionPublished
20110040588VIRTUAL MEETING AGGREGATOR SYSTEM AND METHOD - A meeting aggregator system and method enables the formulation of various meeting plan options, analysis of the return on investment and costs associated with each option. The meeting aggregator system accesses an inventory of meeting facilities (e.g., telepresence facilitites, web conference rooms, conference rooms for live meetings, etc.). The meeting aggregator accesses a variety of data sources and implements custom cost calculations to consider travel costs, cultural factors, environmental factors, travel policies and user preferences. A decision tool provides users access to interactive planning, analysis and resource booking.02-17-2011
20110040591VIRTUAL MEETING AGGREGATOR PRICE COMPARISON SYSTEM AND METHOD - A meeting aggregator system and method enables the formulation of various meeting plan options, analysis of the return on investment and costs associated with each option. The meeting aggregator system accesses an inventory of meeting facilities (e.g., telepresence facilities, web conference rooms, conference rooms for live meetings, etc.). The meeting aggregator accesses a variety of data sources and implements custom cost calculations to consider travel costs, cultural factors, environmental factors, travel policies and user preferences. A decision tool provides users access to interactive planning, analysis and resource booking.02-17-2011

Philip Durocher, Warren, NJ US

Patent application numberDescriptionPublished
20090100620Oral Care Implement With Air Flossing System - An oral care implement with an air flossing system cleans debris from the teeth of a user. The oral care implement may include an oral care region having cleaning elements for engaging oral tissue. A body is provided for gripping the implement. An air source is disposed in the body for proving pressurized air to an air outlet. The air outlet is disposed in the oral care region for injecting the pressurized air to clean debris from the oral tissue.04-23-2009

Todd E. Durocher, Warren, MI US

Patent application numberDescriptionPublished
20080292848MULTILAYER ADHESIVE FOR THERMAL REVERSIBLE JOINING OF SUBSTRATES - One embodiment of the invention includes a multilayer dry adhesive system capable of reversible joining of rigid substrates.11-27-2008