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Dupuis, US
Josee Dupuis, Newton, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20090292002 | NUCLEOTIDE AND AMINO ACID SEQUENCES RELATING TO RESPIRATORY DISEASES AND OBESITY - This invention relates to genes identified from human chromosome 12q23-qter, which are associated with various diseases, including asthma. The invention also relates to the nucleotide sequences of these genes, isolated nucleic acids comprising these nucleotide sequences, and isolated polypeptides or peptides encoded thereby. The invention further relates to vectors and host cells comprising the disclosed nucleotide sequences, or fragments thereof, as well as antibodies that bind to the encoded polypeptides or peptides. Also related are ligands that modulate the activity of the disclosed genes or gene products. In addition, the invention relates to methods and compositions employing the disclosed nucleic acids, polypeptides or peptides, antibodies, and/or ligands for use in diagnostics and therapeutics for asthma and other diseases. | 11-26-2009 |
Josèe Dupuis, Newton, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20110201782 | NOVEL HUMAN GENES RELATING TO RESPIRATORY DISEASES AND OBESITY - This invention relates to isolated nucleic acids comprising genes of human chromosome 12q23-qter and the proteins encoded by these genes. Expression vectors and host cells containing such genes or fragments thereof, as well as antibodies to the proteins encoded by these nucleic acids are also included herein. | 08-18-2011 |
Joseph E. Dupuis, Ledyard, CT US
| Patent application number | Description | Published |
|---|---|---|
| 20100151707 | Electrical connector with separate contact mounting and compensation boards - An electrical connector includes a housing having a plug receiving cavity with an open end for receiving a plug and with an inner end spaced from the open end, and having a forward chamber outside of the cavity and adjacent the open end. A mounting circuit board is in the housing adjacent the inner end. A plurality of pairs of electrical jack contacts have mounting ends engaging the mounting circuit board, plug contacting portions extending through the cavity from the mounting end toward the open end, and free ends extending from the contacting portion into the forward chamber. A compensation circuit board is mounted in the forward chamber of the housing outside of the plug receiving cavity, and has a compensation circuit with conductive pads. The free ends of the jack contacts engage the conductive pads. A spring in the forward chamber biases the compensation circuit board towards the free ends of the jack contacts. | 06-17-2010 |
| 20100151710 | TELECOMMUNICATIONS CONNECTOR PANEL WITH INTERPORT CROSSTALK ISOLATION - A multi-port telecommunications connector panel has an electrically conductive housing that defines a plurality of ports, each with a plug receiving cavity aligned with a respective set of jack contacts. The housing surrounds the sets of jack contacts individually and collectively to separate and isolate adjacent ports. Electrically conductive isolation barriers, which are electrically connected to and may be integral with the housing, separate adjacent sets of insulation displacement contacts, which are arranged in an offset pattern. | 06-17-2010 |
| 20110131805 | Electrical connector with low-stress, reduced-electrical-length contacts - An electrical connector adapted to receive a mating plug utilizes low-profile jack terminal contacts that can flex in their PCB-anchored base portions, which are substantially parallel to the PCB. Any bend in the distal connecting portion or in the intermediate transition portion of each terminal contact is gradual and forms an obtuse angle, thus minimizing stress concentrations. The contacts preferably are arranged in two oppositely facing and interdigitating rows of four contacts each. In one embodiment, the terminal contacts are anchored to the PCB by a contact cradle that constrains the base portion of each terminal contact at two spaced anchoring locations, allowing the base portion to flex therebetween. In another embodiment, the base portions of the terminal contacts are embedded in at least one elastomeric member, which is fitted to the PCB. | 06-09-2011 |
Larry J. Dupuis, Grosse Ile, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20090315364 | A-Pillar Joint for Automotive Vehicles - An A-pillar joint configuration where the front end frame rail members are welded to the A-pillar eliminates the seals at the interface between the front end frame rail members and the A-pillars. The front flange of the A-pillar is also eliminated in the hydroformed configuration while the hydroformed frame rail members are formed with rearward ends that mate with the shape of A-pillar to positioned flattened ends against the exterior vertical side of the A-pillars for welding thereto. The resulting joint configuration eliminates the openings in the A-pillar for the passage of the front end frame rail members requiring seals to insulate the passenger compartment from engine and road noises. | 12-24-2009 |
Lawrence J. Dupuis, Grosse Ile, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20110093107 | Computer-Implemented Method and System for Determining a Material Utilization for Part Assemblies - Various embodiments may include determining a material utilization for one or more assemblies having a plurality of parts. Offal data for one or more parts comprising one or more part assemblies and a blank material utilization status for each of the one or more part assemblies may be received. The blank material utilization status for the one or more part assemblies may be based on a blank material utilization status for each of the one or more parts. The offal data may be standardized to obtain standardized offal data. One or more offal utilization assignments for the part assemblies having a plurality of parts may be determined based on the standardized offal data and the blank material utilization status for the part assemblies. The offal utilization assignments may then be transmitted for assignment to the one or more part assemblies. | 04-21-2011 |
Mark Dupuis, South Burlington, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090206449 | STRESS-MODIFIED DEVICE STRUCTURES, METHODS OF FABRICATING SUCH STRESS-MODIFIED DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT - Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices. | 08-20-2009 |
Mark D. Dupuis, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20100320571 | BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY - A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure. | 12-23-2010 |
Michael P. Dupuis, Westfield, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20110302761 | PROCESS FOR MANUFACTURING AN ANODIZED ALUMINUM DISC SEAL SHELL - A method is provided for manufacturing an anodized disc seal shell for a container. The method includes: providing a metal disc seal shell having a surface; masking a portion of the surface to provide a masked surface and an unmasked surface; anodizing the unmasked surface; and removing the masking from the masked surface to provide an un-anodized surface. | 12-15-2011 |
Nicolas Dupuis, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110150386 | PHOTONIC INTEGRATED CIRCUIT HAVING A WAVEGUIDE-GRATING COUPLER - A photonic integrated circuit (PIC) having a waveguide-grating coupler with two evanescently coupled waveguides. The first waveguide is fabricated using materials suitable for manufacturing active optical elements in the PIC. The second waveguide is fabricated using materials capable of providing a relatively high index-of-refraction contrast for the constituent waveguide grating. The waveguide-grating coupler is compatible with the III-V semiconductor technology while being relatively easy to fabricate on an industrial scale. | 06-23-2011 |
| 20110249938 | OPTICAL GRATING COUPLER - An apparatus includes a crystalline inorganic semiconductor substrate. A planar optical waveguide core is located over the substrate such that a first length of the planar optical waveguide core is directly on the substrate. A regular array of optical scattering structures is located within a second length of the planar optical waveguide core. A cavity is located in the substrate between the regular array and the substrate. | 10-13-2011 |
Patricia S. Dupuis, Medway, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20100033262 | RADIO FREQUENCY INTERCONNECT CIRCUITS AND TECHNIQUES - A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly. | 02-11-2010 |
| 20100066631 | Panel Array - A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components. | 03-18-2010 |
| 20100126010 | Radio Frequency Interconnect Circuits and Techniques - A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly. | 05-27-2010 |
Paul Dupuis, Glendale, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090114286 | PIEZOELECTRIC PRESSURE CONTROL VALVE - A pressure control valve having a common plenum formed by two flow control valves that each utilize electrically controlled piezoelectric actuators to generate a number of possible operating states and thus control an output pressure from the common plenum formed by the two flow control valves. The flow control valves each have at least one pressure fitting and nozzle, and a nozzle orifice sealing mechanism coupled to the piezoelectric actuator. The piezoelectric actuator may be a piezo-ceramic actuator fixed along one side to a chamber of the flow control valve and having a free side opposite the fixed side. Upon receiving a voltage of a desired magnitude and polarity, the free side of the piezo-ceramic actuator and the nozzle orifice sealing mechanism moves to control a fluid flow into the common plenum. By controllably dithering the piezoelectric actuators, the output pressure from the common plenum may be accurately regulated. | 05-07-2009 |
| 20090173387 | PIEZOELECTRIC ACTUATOR WITH A GIMBALLED VALVE - A gimballed valve for a flow control valve operates as a sealing member for an adjustable nozzle and is coupled to a piezoelectric actuator having stacked piezoelectric members that are toroidally shaped. The gimballed valve includes at least two support rings and a center closure member. In one embodiment only an outermost support is in contact with at least one member of the piezoelectric actuator. The support rings may be concentrically arranged and coupled together with flexure members. The center closure member operates to seal against an orifice in the adjustable nozzle and may deflect upon contact with the adjustable nozzle to account for misalignment issues that may arise during machining and/or assembly of the flow control valve. | 07-09-2009 |
Paul B. Dupuis, Phoenix, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090278718 | PRESSURE SENSOR WITH IMPROVED RATE-OF-CHANGE COMPATIBLE DATA OUTPUT - An integrated sensor implementation employs a data acquisition method for producing digital output signals that enables computing low latency, low noise, rate of pressure (or altitude etc.) change measurements. An example sensor includes a self-digitizing pressure and temperature sensor circuit that outputs a serial digital signal that varies with at least one physical parameter to which the sensor circuit is exposed. The sensor incorporates an internal sigma-delta A/D converter and digital data acquisition device that effectively time-stamps all acquired data. This time stamped data is then transmitted to an external processing resource (microprocessor) that is used to convert the self-digitized, time stamped data into low latency, low-noise proportional and rate parameter outputs having the desired engineering units for at least one physical parameter sensed. This low-latency, low noise rate of change signal may be derived without the latency penalty of digital filtering. | 11-12-2009 |
Paul B. Dupuis, Glendale, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20100326530 | PIEZOELECTRIC FLOW CONTROL VALVE - A flow control valve includes an electrically controlled piezoelectric actuator, at least one pressure fitting and nozzle, and a nozzle orifice sealing mechanism coupled to the piezoelectric actuator. The piezoelectric actuator may be a piezo-ceramic actuator fixed along one side to a chamber of the flow control valve and having a free side opposite the fixed side. Upon receiving a voltage of a desired magnitude and polarity, the free side of the piezo-ceramic actuator and the nozzle orifice sealing mechanism moves to control a fluid flow into the chamber. By controllably dithering the piezoelectric actuator of the flow control valve, an output flow from the chamber may be accurately regulated. | 12-30-2010 |
Russell Dean Dupuis, Atlanta, GA US
| Patent application number | Description | Published |
|---|---|---|
| 20100072518 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME - Methods of fabricating semiconductor devices using electrode-less wet-etching techniques to reduce defect densities on etched group III-nitride semiconductor surfaces are described herein. The methods generally involve contacting an etched surface of a component of a semiconductor device with a solution comprising a metal hydroxide and an oxidizing agent effective to reduce a roughness of the etched surface, wherein the etched surface is formed from a composition comprising a nitride of a group III element. Improved semiconductor devices are also disclosed. | 03-25-2010 |