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Dunne, TX
Philip J. Dunne, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110303661 | STORAGE MODULE ADAPTER ASSEMBLY FOR MODULAR CONTAINER - A storage module adapter assembly includes adapter base plates that are two-person portable, can be installed/removed by hand, and cooperate with existing structures of existing modular cargo containers. Each adapter base plate includes various longitudinal and transverse frame members, as well as first and second longitudinal frame members on opposed sides thereof. The first longitudinal frame member has a first height, and the second longitudinal frame member has a second height, which is greater than the first height. Each of the first and second longitudinal frame members also include generally horizontal flange members extending from a top side thereof, such that when two adapter base plates are appropriately positioned side by side, the generally horizontal flange members on the adjacent sides of the two adapter base plates overlap due to the difference between the first and second heights. The adapter base plates can then be connected together by appropriate mechanisms. | 12-15-2011 |
Rajiv Dunne, Murphy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090278244 | IC DEVICE HAVING LOW RESISTANCE TSV COMPRISING GROUND CONNECTION - A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame. | 11-12-2009 |
| 20090289648 | COAXIAL FOUR-POINT PROBE FOR LOW RESISTANCE MEASUREMENTS - Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance. | 11-26-2009 |
| 20090297879 | Structure and Method for Reliable Solder Joints - A solder joint ( | 12-03-2009 |
| 20100159643 | BONDING IC DIE TO TSV WAFERS - A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks. | 06-24-2010 |
| 20110183464 | DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS - A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article. | 07-28-2011 |
Rajiv Dunne, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090278245 | PACKAGED ELECTRONIC DEVICES WITH FACE-UP DIE HAVING TSV CONNECTION TO LEADS AND DIE PAD - A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad. | 11-12-2009 |
Rajiv C. Dunne, Murphy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090014898 | SOLDER CAP APPLICATION PROCESS ON COPPER BUMP USING SOLDER POWDER FILM - A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad. | 01-15-2009 |
Rajiv Carl Dunne, Murphy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090166832 | STACKED FLIP-ASSEMBLED SEMICONDUCTOR CHIPS EMBEDDED IN THIN HYBRID SUBSTRATE - A semiconductor system having a substrate ( | 07-02-2009 |
| 20100159644 | LOW-COST FLIP-CHIP INTERCONNECT WITH AN INTEGRATED WAFER-APPLIED PHOTO-SENSITIVE ADHESIVE AND METAL-LOADED EPOXY PASTE SYSTEM - Various exemplary embodiments provide materials and methods for flip-chip packaging technology. The disclosed flip-chip packaging technology can use a single B-stage wafer-applied photo-sensitive adhesive along with printed interconnects, which does not include conventional underfill materials and processes. In one embodiment, a photo-sensitive adhesive can be applied on a semiconductor die or a base substrate with conductive bumps printed in through-openings of the photo-sensitive adhesive. One or more semiconductor dies can be laterally packaged or vertically stacked on the base substrate using the printed conductive bumps as interconnects there-between. | 06-24-2010 |