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Du Nguyen, Danbury, CT US

Patent application number	Description	Published
20100176513	STRUCTURE AND METHOD OF FORMING METAL INTERCONNECT STRUCTURES IN ULTRA LOW-K DIELECTRICS - A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.	07-15-2010
20110117737	Method of Forming Metal Interconnect Structures in Ultra Low-K Dielectrics - A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.	05-19-2011

Du Randy, Miaoli County TW

Patent application number	Description	Published
20110028234	GOLF CLUB HEAD HAVING SCORE LINE STRUCTURE - A golf club head having score line structure is disclosed to include a club head body that has a recessed portion located on the ball-striking face thereof and supporting ribs and internal grooves alternatively arranged in the recessed portion, and a ball-striking face plate supported on the topmost edges of the supporting ribs in the recessed portion of the club head body and having external score lines arranged on the front face.	02-03-2011

Du Xu, Chengdu CN

Patent application number	Description	Published
20090245269	METHOD AND CORE ROUTER FOR DELAYING BURST - A method and a core router for implementing forward delay for bursts are disclosed. The core router configured with an FDL performs proactive delay processing for the burst to be overlapped after predicting that the burst will be overlapped on the link to be protected, thus reducing the probability of burst conflict on the downstream link to be protected. After finding that burst conflict will occur on the output port of the core router at a future moment, the core router sends a burst delay request to the upstream core router, requesting the upstream core router that has an FDL and the delay capability to delay the burst. Therefore, the FDL configured in the network is brought into full play, and the probability of burst conflict is reduced.	10-01-2009
20090252493	NETWORK NODE, BUFFER DEVICE, AND SCHEDULING METHOD - A buffer device includes at least one internal switching unit and at least one basic buffer unit. The internal switching unit includes at least two inputs and at least two outputs. The internal switching unit and the basic buffer unit form a closed connection by alternating with each other via one input of the two inputs and one output of the two outputs. Another one of the at least two inputs of the internal switching unit receives a light wave. The internal switching unit outputs the light wave according to a first control signal. The basic buffer unit buffers the light wave from the internal switching unit. At the same time, a network node and a scheduling method are also provided. A network node with the buffer device has a small scale and is easy to realize, while the data packet loss rate is decreased and the head of line blocking is avoided.	10-08-2009

Du Yangzhou, Beijing CN

Patent application number	Description	Published
20090169065	Detecting and indexing characters of videos by NCuts and page ranking - Apparatuses, systems, and computer program products that detect and/or index characters of videos are disclosed. One or more embodiments comprise an apparatus an apparatus having a feature extraction module and a cast indexing module. The feature extraction module may extract features of a scale invariant feature transform (SIFT) for face sets of a video and the cast indexing module may detect one or more characters of the video via one or more associations of clusters of the features. Some alternative embodiments may include a cast ranking module to sort characters of the video, considering such factors as appearance times of the characters, appearance frequencies of the characters, and page rankings of the characters. The apparatus may associate or partition the clusters based on a normalized cut process, as well as detect the characters based on measures of distances of nodes associated with the features. Numerous embodiments may detect the characters based upon partitioning the clusters via solutions for eigenvalue systems for matrices of nodes of the clusters.	07-02-2009

Du Yaosheng, Chaoyang District Beijing CN

Patent application number	Description	Published
20090027821	INTEGRATED THERMISTOR AND METALLIC ELEMENT DEVICE AND METHOD - A circuit protection device includes a fuse element placed in parallel with a PTC thermistor layer. The element and PTC thermistor layer are provided on one or more insulating substrate, such as an FR-4 or polyimide substrate. First and second conductors connect the fuse element and PTC thermistor layer electrically in parallel, such that current (i) initially under normal flows mainly through the fuse element and PTC thermistor layer at a lower drop in voltage and (ii) after an opening of the fuse element flows under normal operation through the PTC thermistor layer at a higher drop in voltage.	01-29-2009