Patent application number | Description | Published |
20100236613 | Single Heterojunction Back Contact Solar Cell - A back contact single heterojunction solar cell and associated fabrication process are provided. A first semiconductor substrate is provided, lightly doped with a first dopant type. The substrate has a first energy bandgap. A second semiconductor is formed over a region of the substrate backside. The second semiconductor has a second energy bandgap, larger than the first energy bandgap. A third semiconductor layer is formed over the first semiconductor substrate topside, moderately doped with the first dopant and textured. An emitter is formed in the substrate backside, heavily doped with a second dopant type, opposite of the first dopant type, and a base is formed in the substrate backside, heavily doped with the first dopant type. Electrical contacts are made to the base and emitter. Either the emitter or base is formed in the second semiconductor. | 09-23-2010 |
20100276776 | Germanium Film Optical Device Fabricated on a Glass Substrate - A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes. | 11-04-2010 |
20110068342 | Laser Process for Minimizing Variations in Transistor Threshold Voltages - A laser method is provided for minimizing variations in transistor threshold voltages. The method supplies a wafer with a laser-crystallized active semiconductor film having a top surface with a first surface roughness. The method laser anneals the active semiconductor film, and in response to the laser annealing, melts the top surface of the active semiconductor film. The result is a top surface with a second roughness, less than the first roughness. More explicitly, the wafer active semiconductor film is crystallized using a laser with a first fluence, and then laser annealed with a second fluence, less than the first fluence. As compared with complementary metal-oxide-semiconductor field-effect (CMOSFET) thin-film transistor (TFT) structures formed in unprocessed regions of the active semiconductor film, the TFT threshold voltage standard deviation for TFTs in laser annealed portions of the active film are 60% less for n-channel and 30% less for p-channel TFTs. | 03-24-2011 |
20110163404 | Germanium Film Optical Device - A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes. | 07-07-2011 |
Patent application number | Description | Published |
20100059892 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, PRODUCTION METHOD OF DISPLAY DEVICE, SEMICONDUCTOR DEVICE, PRODUCTION METHOD OF SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT - The present invention provides a production method of a semiconductor device, a production method of a display device, a semiconductor device, a production method of a semiconductor element, and a semiconductor element, each capable of providing a lower-resistance semiconductor element which is more finely prepared through more simple steps. The production method of the semiconductor device of the present invention is a production method of a semiconductor device including a semiconductor element on a substrate, wherein the production method includes a metal silicide-forming step of: transferring the semiconductor element onto the substrate, the semiconductor element having a multilayer structure of a silicon layer and a metal layer, and by heating, forming metal silicide from silicon for a metal layer-side part of the silicon layer and metal for a silicon layer-side part of the metal layer. | 03-11-2010 |
20100270618 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The present invention provides a production method of a semiconductor device, capable of improving surface flatness of a semiconductor chip formed on a semiconductor substrate and thereby suppressing a variation in electrical characteristics of the semiconductor chip transferred onto a substrate with an insulating surface, and further capable of improving production yield. The present invention provides a production method of a semiconductor device including a semiconductor chip on a substrate with an insulating surface, the semiconductor chip having a conductive pattern film,
| 10-28-2010 |
20120155038 | FLEXIBLE CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board ( | 06-21-2012 |