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Drapkin

Evgeny Drapkin, Delafield, WI US

Patent application numberDescriptionPublished
20090169085METHOD AND APPARATUS FOR IMAGE RECONSTRUCTION USING DATA DECOMPOSITION FOR ALL OR PORTIONS OF THE PROCESSING FLOW - A method and apparatus for processing raw image data to create processed images. Raw image data is acquired. The raw image data is decomposed by a data decomposer into N subsets of raw image data. The number N is based on a number of available image generation processors. The N subsets of raw image data are processed by at least one image generation processor to create processed image data. If more than one image generation processor is available, the image generation processors perform image processing on the raw image data in parallel with respect to each other.07-02-2009

Oleg Drapkin, Richmond Hill CA

Patent application numberDescriptionPublished
20080284468METHOD AND APPARATUS FOR CONTROLLING A COMMUNICATION SIGNAL BY MONITORING ONE OR MORE VOLTAGE SOURCES - An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.11-20-2008
20090086865Differential Signal Comparator - A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.04-02-2009
20090133252Chip Capacitor - Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.05-28-2009
20100149701ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD - A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants. In addition, an ESD feedback circuit is employed in conjunction with control logic to suitably control the ESD control logic during an ESD event. Circuitry is also used during a power up event to render the shunt structure non-conductive.06-17-2010
20100161261Method and Apparatus for Integrated Circuit Temperature Control - A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element, wherein the third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage; and calculating an error corrected difference between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.06-24-2010
20100176848INPUT/OUTPUT BUFFER CIRCUIT - A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.07-15-2010

Patent applications by Oleg Drapkin, Richmond Hill CA

Olge Drapkin, Richmond Hill CA

Patent application numberDescriptionPublished
20090323437Method and Apparatus for Data Inversion in Memory Device - The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.12-31-2009

Paola T. Drapkin, Iowa City, IA US

Patent application numberDescriptionPublished
20080318320TARGETING VECTOR TO THE UROKINASE PLASMINOGEN ACTIVATOR RECEPTOR - The present invention relates to the targeted delivery of a delivery vehicle construct which specifically binds to and stimulates endocytosis into cells expressing the urokinase plasminogen activator receptor (uPAR), and particularly human airway epithelia. The delivery vehicle construct comprises a portion of uPA and a cargo linked thereto and is useful for the targeted delivery of the cargo to a cell. In one aspect of the invention, the uPA portion of the delivery vehicle construct comprises the wild-type uPA, a fragment of uPA which has the PAI-1 binding region deleted, or a uPA peptide comprising amino acids 13-19 and is useful for the targeted delivery of the cargo to cells, and in particular to airway epithelia. The present invention also provides a method for delivering the delivery vehicle construct to a cell. The method comprises the steps of (a) contacting a target cell with a delivery vehicle construct comprising a uPA portion and a cargo portion; and (b) obtaining a desired result in the target cell.12-25-2008

Ronny Drapkin, Newton, MA US

Patent application numberDescriptionPublished
20080286199Methods of Detecting Ovarian Cancer - The present invention provides methods of detecting ovarian cancer using biomarkers.11-20-2008

Stanislav Drapkin, Richmond Hill CA

Patent application numberDescriptionPublished
20080270153SERVICE ORIENTED ARCHITECTURE (SOA) LIFECYCLE MODEL MIGRATION - Embodiments of the present invention address deficiencies of the art in respect to SOA systems migration and provide a method, system and computer program product for SOA lifecycle model migration. In one embodiment of the invention, a method for migrating a process model in a monolithic application to an SOA lifecycle model in an SOA based system can be provided. The method can include selecting process steps implemented by code assets in a code base for the monolithic application, mapping the selected process steps to corresponding ones of the code assets, and determining entry and exit points in the code assets for establishing callbacks into services defining the SOA based system. Thereafter, callbacks to the determined entry and exit points can be established and the services can be deployed.10-30-2008