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| 20080270862 | METHOD AND APPARATUS FOR SOFT-ERROR IMMUNE AND SELF-CORRECTING LATCHES - A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system. | 10-30-2008 |
| 20080288196 | Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities - Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa. | 11-20-2008 |
| 20080288197 | Calibration of Multi-Metric Sensitive Delay Measurement Circuits - A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits. | 11-20-2008 |
| 20090037798 | SELF-RESETTING, SELF-CORRECTING LATCHES - A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds). | 02-05-2009 |
| 20090144006 | CALIBRATION OF MULTI-METRIC SENSITIVE DELAY MEASUREMENT CIRCUITS - A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits. | 06-04-2009 |
| 20100102854 | CIRCULAR EDGE DETECTOR - A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell. | 04-29-2010 |
| 20100271057 | Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit - A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node. | 10-28-2010 |
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| 20100078222 | MATRIX TURBINE SLEEVE AND METHOD FOR MAKING SAME - A turbine matrix sleeve in accordance with the invention includes an inner cylindrical structure made up of a first material. The inner cylindrical structure may include multiple blades and multiple channels running between the blades along an outside diameter thereof. The inner cylindrical structure further includes threads, such as right-hand or left-hand threads, on an outer surface thereof. An outer layer, made up of a second material different from the first material, is integrally bonded to the threads. This outer layer may be optionally embedded with hardened inserts or buttons, such as PDC inserts, diamond inserts, TSP inserts, or the like. The threaded surface on the inner cylindrical structure significantly improves the bond between the outer layer and the inner cylindrical structure and creates a mechanical lock therebetween. | 04-01-2010 |
| 20110031028 | Hard Composite with Deformable Constituent and Method of Applying to Earth-Engaging Tool - A hardmetal composite used as wear-resistant surfaces and inlays in earth-engaging equipment includes more than one hardphase. At least one hardphase has a high average particle size, for example, from 100 μm to 2000 μm. The hardphases vary in terms of particle size, hardness, and binder content, and at least one hardphase includes a particulate constituent capable of plastic deformation that comprises at least 1% residual porosity. | 02-10-2011 |
