Patent application number | Description | Published |
20080270862 | METHOD AND APPARATUS FOR SOFT-ERROR IMMUNE AND SELF-CORRECTING LATCHES - A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system. | 10-30-2008 |
20080288196 | Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities - Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa. | 11-20-2008 |
20080288197 | Calibration of Multi-Metric Sensitive Delay Measurement Circuits - A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits. | 11-20-2008 |
20090037798 | SELF-RESETTING, SELF-CORRECTING LATCHES - A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds). | 02-05-2009 |
20090144006 | CALIBRATION OF MULTI-METRIC SENSITIVE DELAY MEASUREMENT CIRCUITS - A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits. | 06-04-2009 |
20100102854 | CIRCULAR EDGE DETECTOR - A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell. | 04-29-2010 |
20100271057 | Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit - A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node. | 10-28-2010 |
20130268785 | Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation - A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated. | 10-10-2013 |
20130268786 | Minimizing Power Consumption for Fixed-Frequency Processing Unit Operation - A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated. | 10-10-2013 |
20130307656 | Stacked Through-Silicon Via (TSV) Transformer Structure - A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding. | 11-21-2013 |
20140218087 | Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal. | 08-07-2014 |
20140223210 | Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode. | 08-07-2014 |
20140237302 | CHARACTERIZATION AND FUNCTIONAL TEST IN A PROCESSOR OR SYSTEM UTILIZING CRITICAL PATH MONITOR TO DYNAMICALLY MANAGE OPERATIONAL TIMING MARGIN - Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller. | 08-21-2014 |
20140244212 | Monitoring Aging of Silicon in an Integrated Circuit Device - A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement. | 08-28-2014 |
20150081039 | Dynamic Adjustment of Operational Parameters to Compensate for Sensor Based Measurements of Circuit Degradation - A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified. | 03-19-2015 |
20150081044 | Dynamic Adjustment of Operational Parameters to Compensate for Sensor Based Measurements of Circuit Degradation - A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified. | 03-19-2015 |
20150094995 | Managing Interconnect Electromigration Effects - A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent. | 04-02-2015 |
20150234422 | Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution - A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode. | 08-20-2015 |
Patent application number | Description | Published |
20120005513 | PERFORMANCE CONTROL OF FREQUENCY-ADAPTING PROCESSORS BY VOLTAGE DOMAIN ADJUSTMENT - A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance. | 01-05-2012 |
20120043982 | CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION - A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay. | 02-23-2012 |
20130113448 | COIL INDUCTOR FOR ON-CHIP OR ON-CHIP STACK - A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided. | 05-09-2013 |
20150046721 | RECONFIGURABLE CIRCUIT TO EMULATE SYSTEM CRITICAL PATHS - A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source. | 02-12-2015 |
Patent application number | Description | Published |
20100078222 | MATRIX TURBINE SLEEVE AND METHOD FOR MAKING SAME - A turbine matrix sleeve in accordance with the invention includes an inner cylindrical structure made up of a first material. The inner cylindrical structure may include multiple blades and multiple channels running between the blades along an outside diameter thereof. The inner cylindrical structure further includes threads, such as right-hand or left-hand threads, on an outer surface thereof. An outer layer, made up of a second material different from the first material, is integrally bonded to the threads. This outer layer may be optionally embedded with hardened inserts or buttons, such as PDC inserts, diamond inserts, TSP inserts, or the like. The threaded surface on the inner cylindrical structure significantly improves the bond between the outer layer and the inner cylindrical structure and creates a mechanical lock therebetween. | 04-01-2010 |
20110031028 | Hard Composite with Deformable Constituent and Method of Applying to Earth-Engaging Tool - A hardmetal composite used as wear-resistant surfaces and inlays in earth-engaging equipment includes more than one hardphase. At least one hardphase has a high average particle size, for example, from 100 μm to 2000 μm. The hardphases vary in terms of particle size, hardness, and binder content, and at least one hardphase includes a particulate constituent capable of plastic deformation that comprises at least 1% residual porosity. | 02-10-2011 |
20150107908 | HARD COMPOSITE WITH DEFORMABLE CONSTITUENT AND METHOD OF APPLYING TO EARTH-ENGAGING TOOL - A hardmetal composite used as wear-resistant surfaces and inlays in earth-engaging equipment includes more than one hardphase. At least one hardphase has a high average particle size, for example, from 100 μm to 2000 μm. The hardphases vary in terms of particle size, hardness, and binder content, and at least one hardphase includes a particulate constituent capable of plastic deformation that comprises at least 1% residual porosity. | 04-23-2015 |
Patent application number | Description | Published |
20080291465 | NON-DESTRUCTIVE INSPECTION USING LASER-ULTRASOUND AND INFRARED THERMOGRAPHY - An inspection system is provided to examine internal structures of a target material. This inspection system includes a generation laser, an ultrasonic detection system, a thermal imaging system, and a processor/control module. The generation laser produces a pulsed laser beam that is operable to induce ultrasonic displacements and thermal transients at the target material. The ultrasonic detection system detects ultrasonic surface displacements at the target material. The thermal imaging system detects thermal transients at the target material. The processor analyzes both detected ultrasonic displacements and thermal imagery of the target material to yield information about the target material's internal structure. | 11-27-2008 |
20090290163 | Laser Ultrasonic Measurement System With Movable Beam Delivery - A laser ultrasonic measurement system includes a first and a second laser source configured to generate a first and a second laser beam, respectively. A movable mechanical link is arranged to transmit the first laser beam. The movable mechanical link is formed by a plurality of rigid sections interconnected by rotating joints. A robot is configured to support and control the movement of at least a section of the mechanical link to transmit the first laser beam to an object. An optical scanner is positioned proximate to the mechanical link. The optical scanner is configured to direct the first and second laser beams onto the object. An interferometer is optically coupled to the optical scanner. The interferometer is configured to receive reflected light from the object and in response generate an electrical signal. The first laser source is kinematically mounted in a housing assembly. | 11-26-2009 |
20090290166 | Adjustable Interferometer for Laser Ultrasonic Measurement - An interferometer includes a cavity including a pair of mirrors defining a cavity length. An input beam and a counter-propagating reference beam are directed into the cavity. The interferometer generates a feedback control signal and an ultrasound signal for optimal performance and measurement of a target, respectively. | 11-26-2009 |
20120320383 | Enclosed Laser-Ultrasonic Inspection System - A laser ultrasonic inspection system comprises laser sources configured to generate laser beams, an optical scanner configured to direct the laser beams onto an object thereby generating ultrasonic waves in the object and illuminating the object, an interferometer configured to generate an electrical signal in response to the reflected light, and a radiation restricting inspection chamber for housing the object. Another laser ultrasonic inspection system comprises a radiation restricting inspection chamber, laser sources located outside of the inspection chamber, an optical scanner located inside the inspection chamber, a visible laser tracer representative of the orientation of the laser beams; an interferometer, a scanner positioning mechanism, and an object positioning mechanism. A method for inspecting an object comprises the steps of positioning an object inside of an inspection chamber, defining a scanning profile, and directing laser beams onto the object according to the inspection profile. | 12-20-2012 |
20130120758 | LASER ULTRASONIC MEASUREMENT SYSTEM WITH MOVABLE BEAM DELIVERY - A laser ultrasonic measurement system includes a first and a second laser source configured to generate a first and a second laser beam, respectively. A movable mechanical link is arranged to transmit the first laser beam. The movable mechanical link is formed by a plurality of rigid sections interconnected by rotating joints. A robot is configured to support and control the movement of at least a section of the mechanical link to transmit the first laser beam to an object. An optical scanner is positioned proximate to the mechanical link. The optical scanner is configured to direct the first and second laser beams onto the object. An interferometer is optically coupled to the optical scanner. The interferometer is configured to receive reflected light from the object and in response generate an electrical signal. The first laser source is kinematically mounted in a housing assembly. | 05-16-2013 |