Patent application number | Description | Published |
20100188663 | SUB-MICRON SURFACE PLASMON RESONANCE SENSOR SYSTEMS - A sensor for detecting the presence of a target analyte, ligand or molecule in a test fluid, comprising a light transmissive substrate on which an array of surface plasmon resonant (SPR) elements is mounted is described. A multi-channel sensor for detecting the presence of several targets with a single microchip sensor is described. A multi-channel sensor including collections of SPR elements which are commonly functionalized to one of several targets is also described. The detectors sense changes in the resonant response of the SPR elements indicative of binding with the targets. | 07-29-2010 |
20100188664 | SUB-MICRON SURFACE PLASMON RESONANCE SENSOR SYSTEMS - A sensor for detecting the presence of a target analyte, ligand or molecule in a test fluid, comprising a light transmissive substrate on which an array of surface plasmon resonant (SPR) elements is mounted is described. A multi-channel sensor for detecting the presence of several targets with a single micro-chip sensor is described. A multi-channel sensor including collections of SPR elements which are commonly functionalized to one of several targets is also described. The detectors sense changes in the resonant response of the SPR elements indicative of binding with the targets. | 07-29-2010 |
20100189603 | SUB-MICRON SURFACE PLASMON RESONANCE SENSOR SYSTEMS - A sensor for detecting the presence of a target analyte, ligand or molecule in a test fluid, comprising a light transmissive substrate on which an array of surface plasmon resonant (SPR) elements is mounted is described. A multi-channel sensor for detecting the presence of several targets with a single microchip sensor is described. A multi-channel sensor including collections of SPR elements which are commonly functionalized to one of several targets is also described. The detectors sense changes in the resonant response of the SPR elements indicative of binding with the targets. | 07-29-2010 |
20100290309 | COMPACT MICROFLUIDIC STRUCTURES FOR MANIPULATING FLUIDS - Disclosed is a method and apparatus for manipulating fluids. The apparatus may include a microfluidic structure including inlet channels ( | 11-18-2010 |
20110228277 | SUB-MICRON SURFACE PLASMON RESONANCE SENSOR SYSTEMS - A sensor for detecting the presence of a target analyte, ligand or molecule in a test fluid, comprising a light transmissive substrate on which an array of surface plasmon resonant (SPR) elements is mounted is described. A multi-channel sensor for detecting the presence of several targets with a single microchip sensor is described. A multi-channel sensor including collections of SPR elements which are commonly functionalized to one of several targets is also described. The detectors sense changes in the resonant response of the SPR elements indicative of binding with the targets. | 09-22-2011 |
20110257494 | SUB-MICRON SURFACE PLASMON RESONANCE SENSOR SYSTEMS - Wearable or implantable devices combining microfluidic control of sample and reagent flow and micro-cavity surface plasmon resonance sensors functionalized with surface treatments or coatings capable of specifically binding to target analytes, ligands, or molecules in a bodily fluid are provided. The devices can be used to determine the presence and concentration of target analytes in the bodily fluids and thereby help diagnose, monitor or detect changes in disease conditions. | 10-20-2011 |
20130004469 | ENGINEERED LUMENIZED VASCULAR NETWORKS AND SUPPORT MATRIX - Disclosed herein are capillary fabrication devices comprising living cells within a support medium. Culture of the cells produces viable lumenized capillary networks with natural or pre-determined geometries and ECM and basement membrane associated with the capillary networks. The capillary networks and the ECM and basement membrane detachable from the capillary networks are useful for tissue engineering applications. | 01-03-2013 |
Patent application number | Description | Published |
20090260015 | SOFTWARE PIPELINING - A software pipelining method for generating a schedule for executing a plurality of instructions on a processor, the plurality of instructions involving one or more variables, the processor having one or more physical registers, the method comprising the step of scheduling each of the plurality of instructions, determining whether there is a variable for which there is less than a threshold number of physical registers to which that variable may be allocated, and unscheduling a currently scheduled instruction when there is a variable for which there is less than the threshold number of a physical registers to which that that variable may be allocated. | 10-15-2009 |
20130139135 | OPTIMIZATION METHOD FOR COMPILER, OPTIMIZER FOR A COMPILER AND STORAGE MEDIUM STORING OPTIMIZING CODE - The invention pertains to an optimization method for a compiler, comprising providing a model of inter-operand constraints of physical registers of a target-platform of a compilation; and a) providing an intermediate representation of a source code using virtual registers; b) grouping the virtual registers of the intermediate representation based on the model of inter-operand constraints into two or more groups, each group comprising at least one virtual register; c) if for at least one group at least one interference of virtual registers within the group occurs, amending the intermediate representation to resolve at least one interference and jumping to step b); otherwise d) providing a representation of a group interference graph of interferences between the groups; and e) allocating virtual registers to physical registers using a coloring scheme on the representation of the group interference graph. The invention also refers to a corresponding optimizer for a compiler and a computer-readable storage medium storing optimizing code. | 05-30-2013 |
20150082284 | Method and system for generating a memory trace of a program code executable on a programmable target - A method of generating an instrumented code from a program code executable on a programmable target is described. The method comprises analysing the program code to detect a loop nest with regular memory access in the program code, providing a record of static memory address information associated with the loop nest, and instrumenting the program code to provide an instrumented code corresponding to the program code supplemented with an instrumentation instruction to output an information message comprising a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest. | 03-19-2015 |
Patent application number | Description | Published |
20090009248 | INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF - A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals. | 01-08-2009 |
20090147885 | MAJORITY DETECTOR APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results. | 06-11-2009 |
20090174455 | EXPLICIT SKEW INTERFACE FOR MITIGATING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE - Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise. | 07-09-2009 |
20100013512 | APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST - A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed. | 01-21-2010 |
20100188058 | Reference Voltage Generation for Single-Ended Communication Channels - An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq. | 07-29-2010 |
20100231300 | INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF - A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals. | 09-16-2010 |
20110267092 | APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST - A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed. | 11-03-2011 |
20120114087 | EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE - Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise. | 05-10-2012 |
20130094615 | EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE - Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise. | 04-18-2013 |
20130142285 | MAJORITY DETECTOR APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including, for example,a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results. | 06-06-2013 |
20140049244 | Reference Voltage Generation for Single-Ended Communication Channels - An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq. | 02-20-2014 |
20140269118 | INPUT BUFFER APPARATUSES AND METHODS - Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a second differential amplifier to amplify the input signal into a second output signal that is complementary to the first output signal, and a feedback resistance coupled between the first output signal and the second output signal. Additional apparatuses and methods are described. | 09-18-2014 |
20150116034 | INPUT BUFFER APPARATUSES AND METHODS - Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a second differential amplifier to amplify the input signal into a second output signal that is complementary to the first output signal, and a feedback resistance coupled between the first output signal and the second output signal. Additional apparatuses and methods are described. | 04-30-2015 |