| Patent application number | Description | Published |
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| 20080277701 | High energy implant photodiode stack - An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multifunction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set. | 11-13-2008 |
| 20080280426 | Gallium nitride-on-silicon interface - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al | 11-13-2008 |
| 20080296616 | Gallium nitride-on-silicon nanoscale patterned interface - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al | 12-04-2008 |
| 20080296625 | Gallium nitride-on-silicon multilayered interface - A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process. | 12-04-2008 |
| 20080315255 | Thermal Expansion Transition Buffer Layer for Gallium Nitride on Silicon - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness. | 12-25-2008 |
| 20090008647 | Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers - A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al | 01-08-2009 |
| 20090173933 | Thermal Sensor with a Silicon/Germanium Superlattice Structure - A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate. | 07-09-2009 |
| 20090194800 | Dual-Pixel Full Color CMOS Imager with Large Capacity Well - A dual-pixel full color CMOS imager is provided. The imager comprises a two-photodiode stack including an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer at a first depth overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The imager further includes a single photodiode including a bottom p doped layer overlying the substrate at a third depth, where the third depth is less than, or equal to the first depth. A bottom n doped layer overlies the bottom p doped layer, a top p doped layer directly overlies the bottom n doped layer without an intervening layer, and a top n doped layer overlies the top p doped layer. | 08-06-2009 |
| 20090200584 | Full Color CMOS Imager Filter - A full color complementary metal oxide semiconductor (CMOS) imaging circuit is provided. The imaging circuit comprises an array of photodiodes including a plurality of pixel groups. Each pixel group supplies 3 electrical color signals, corresponding to 3 detectable colors. The circuit also includes a color filter array overlying the photodiode array employing less than 3 separate filter colors. Each pixel group may be enabled as a dual-pixel including a single photodiode (PD) to supply a first color signal and stacked PDs to supply a second and third color signal. In one aspect, the color filter array employs 1 filter color per pixel group. In another aspect, the color filter array employees 2 filter colors per pixel group. In either aspect, the color filter array forms a checkerboard pattern of color filter pixels. For example, a magenta color filter may overlie the stacked PDs of each dual-pixel, to name one variation. | 08-13-2009 |
| 20100090110 | Ge Imager for Short Wavelength Infrared - A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface. | 04-15-2010 |
| 20100102366 | Integrated Infrared and Color CMOS Imager Sensor - An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array is provided. The array is built upon a lightly doped p doped silicon (Si) substrate. Each pixel cell includes at least one visible light detection pixel and an IR pixel. Each visible light pixel includes a moderately p doped bowl with a bottom p doped layer and p doped sidewalls. An n doped layer is enclosed by the p doped bowl, and a moderately p doped surface region overlies the n doped layer. A transfer transistor has a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region. The IR pixel is the same, except that there is no bottom p doped layer. An optical wavelength filter overlies the visible light and IR pixels. | 04-29-2010 |
| 20100104178 | Methods and Systems for Demosaicing - Aspects of the present invention are related to systems and methods for image demosaicing. | 04-29-2010 |
| 20110075245 | Full Color Range Interferometric Modulation - A full color range analog controlled interferometric modulation device is provided. The device includes a transparent substrate, and a transparent fixed-position electrically conductive electrode with a bottom surface overlying the substrate. A transparent spacer overlies the fixed-position electrode, and an induced absorber overlies the spacer. An optically reflective electrically conductive moveable membrane overlies the induced absorber. A cavity is formed between the induced absorber and the moveable membrane having a maximum air gap dimension less than the spacer thickness. In one aspect, the distance from the top surface of the fixed-position electrode to a cavity lower surface is at least twice as great as the cavity maximum air gap dimension. In another aspect, at least one anti-reflective coating (ARC) layer is interposed between the substrate and the fixed-position electrode, and at least one ARC layer is interposed between the fixed-position electrode and the spacer. | 03-31-2011 |
