| Patent application number | Description | Published |
|---|
| 20100106754 | Hardware and Operating System Support for Persistent Memory On A Memory Bus - Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described. | 04-29-2010 |
| 20100106895 | Hardware and Operating System Support For Persistent Memory On A Memory Bus - Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described. | 04-29-2010 |
| 20100332812 | METHOD, SYSTEM AND COMPUTER-ACCESSIBLE MEDIUM FOR LOW-POWER BRANCH PREDICTION - Examples of a method, system, and computer-accessible medium are provided which can utilize a neural branch predictor on, e.g., an analog circuit. For example, a current summation can be used instead of the digital dot-product generally used in traditional neural predictor designs. A scaling factor may also be used to increase prediction accuracy. | 12-30-2010 |
| 20110087845 | BURST-BASED CACHE DEAD BLOCK PREDICTION - The present disclosure generally relates to cache memory systems and/or techniques to identify dead cache blocks in cache memory systems. Example systems may include a cache memory that is accessible by a cache client. The cache memory may include a plurality of storage locations for a first cache block, with a most recently used position location in the cache memory. A cache controller may be configured to predict whether the first cache block stored in the cache memory is identified as a dead cache block based on a cache burst of the first cache block. The cache burst may comprise a first access of the first cache block by a cache client and any subsequent contiguous accesses of the first cache block following the first access by the cache client while the first cache block is in a most recently used position of the cache set. | 04-14-2011 |
| Patent application number | Description | Published |
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| 20100146209 | METHOD AND APPARATUS FOR COMBINING INDEPENDENT DATA CACHES - Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change. | 06-10-2010 |
| 20100146249 | Control-Flow Prediction Using Multiple Independent Predictors - The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods. | 06-10-2010 |
| 20100325395 | DEPENDENCE PREDICTION IN A MEMORY SYSTEM - Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to execute the load operation based upon a prediction type associated with each of the states and a corresponding precedent to the load operation for the associated prediction type. The state-machine may further determine the prediction type for a subsequent load operation based on a result of the load operation. The states of the state machine may correspond to prediction types, which may be a conservative prediction type, an aggressive prediction type, or one or more N-store prediction types, for example. | 12-23-2010 |
| 20110060889 | METHOD, SYSTEM AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING A DISTRIBUTED PREDICATE PREDICTION - Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence predicates, while minimizing the communication between the cores. | 03-10-2011 |
| 20110072239 | DATA MULTICASTING IN A DISTRIBUTED PROCESSOR SYSTEM - Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions. | 03-24-2011 |
