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Doong, TW
Chung-Jae Doong, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100293320 | METHOD AND APPARATUS FOR BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY - Techniques are described herein for managing data in a block-based flash memory device which avoid the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. In addition, the block-based flash memory can emulate both programming and erasing on a byte-by-byte basis, like that provided by an EEPROM. | 11-18-2010 |
Kelvin Yih-Yuh Doong, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080209381 | SHALLOW TRENCH ISOLATION DUMMY PATTERN AND LAYOUT METHOD USING THE SAME - A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed. | 08-28-2008 |
| 20100252907 | Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same - A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed. | 10-07-2010 |
Lih-Ming Doong, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090051019 | Multi-chip module package - A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers. | 02-26-2009 |
Lih-Ming Doong, Zhunan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110221047 | FLIP CHIP PACKAGE STRUCTURE WITH HEAT DISSIPATION ENHANCEMENT AND ITS APPLICATION - A flip chip package structure includes a chip placed under a lead frame, a bump on the upper surface of the chip that is electrically connected to the lead of the lead frame, and a backside metal on the lower surface of the chip that is exposed outside an encapsulant encapsulating the chip and a portion of the lead frame. | 09-15-2011 |
Meng-Syuan Doong, Jhongli City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080305354 | Filler Composition for Welding onto a Substrate - A filler composition for welding onto a substrate is composed of 82.5˜96.5 wt %, aluminum, 3.0˜10.0 wt % copper, 0.2˜1.5 wt % magnesium, 0.1˜1.5 wt % silver, 0.1˜2.0 wt % scandium, 0˜1.5 wt % zirconium, and 0˜1.0 wt % titanium, and can be welded with a high success rate to a substrate (such as an aluminum-copper alloy substrate) and avoiding a hot cracking phenomenon and a low welding strength, so as to achieve the effects of enhancing the yield rate and lowering the cost of a product. | 12-11-2008 |
Yih-Yuh Doong, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090002012 | Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated. | 01-01-2009 |
| 20090187866 | Electrical Parameter Extraction for Integrated Circuit Design - A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver. | 07-23-2009 |
| 20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
| 20100045325 | Test Pad Design for Reducing the Effect of Contact Resistances - An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected. | 02-25-2010 |
| 20100156453 | Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated. | 06-24-2010 |
| 20110168995 | Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated. | 07-14-2011 |