Patent application number | Description | Published |
20080205177 | LAYOUT STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE HAVING IOSA - Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output lines have less loading and therefore enable higher-speed data transfer rates. Some embodiments of the invention include column selection line repeaters between the two memory blocks. The column selection line repeaters reduce loading in the column selection lines, and increase column selection speed. Embodiments of the invention include both input/output sense amplifiers and column selection line repeaters disposed between the two memory blocks to increase data transfer rates on the global input/output lines and also increase column selection speed. | 08-28-2008 |
20090207674 | DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period. | 08-20-2009 |
20100301894 | SEMICONDUCTOR DEVICE CAPABLE OF VERIFYING RELIABILITY - A semiconductor device includes an integrated semiconductor circuit unit, a chip guard-ring disposed along an outer portion of the semiconductor device, and a reliability verifying unit disposed between the integrated semiconductor circuit unit and the chip guard-ring. The reliability verifying unit is configured to delay a reliability verifying signal to detect a fault while in a reliability detecting mode. | 12-02-2010 |
20110090746 | DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period. | 04-21-2011 |
20110128797 | SENSE AMPLIFYING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier. | 06-02-2011 |
20110267915 | ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE - Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer. | 11-03-2011 |
20120213018 | DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period. | 08-23-2012 |
20130242643 | SEMICONDUCTOR MEMORY DEVICE INCLUDING POWER DECOUPLING CAPACITOR - A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer. | 09-19-2013 |
Patent application number | Description | Published |
20080239643 | DISPLAY DEVICE - A display devise includes a display panel and a chassis base supporting the display panel. At least one reinforcing member is attached to the chassis base to add rigidity to the chassis base and at least one stand is attached to the chassis base to allow the chassis base to stand upright. A guide stand couples the reinforcing member to the stand, the guide stand comprising a body and a reinforcing plate substantially extending at an angle from the body. | 10-02-2008 |
20130294008 | MULTILAYER ELECTRONIC COMPONENTS AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a multilayer electronic component having a structure in which a dielectric layer and an internal electrode layer are alternately laminated, which includes the dielectric layer and the internal electrode layer including metal powder and an inhibitor, wherein the inhibitor includes 0.5 to 20 mol % of a Ca component based on 100 mol % of a barium titanate (BT) base material, and a method for manufacturing the same. | 11-07-2013 |
20140020942 | LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF - A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes covering end portions of the ceramic body in length direction; an active layer in which the internal electrodes are disposed in opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in thickness direction, the lower cover layer thicker than the upper cover layer. | 01-23-2014 |
20140240897 | MULTILAYER CERAMIC DEVICE - Disclosed herein is a multilayer ceramic device, including a device body having a plurality of dielectric sheets stacked on one another, the device body having spaced-apart sides and circumferential surfaces connecting the sides; internal electrodes formed on the dielectric sheets; an external electrode having a front portion to cover the sides and a band portion to extend from the front portion to cover parts of the circumferential surfaces; and a reinforcement pattern having a plurality of metal patterns arranged facing one another between the internal electrodes and the circumferential surfaces, wherein a distance between the metal patterns may be smaller than thicknesses of the dielectric sheets on which the internal electrodes are formed. | 08-28-2014 |
20140240899 | MULTILAYER CERAMIC DEVICE - Disclosed herein is a multilayer ceramic device, including a device body; an inner electrode arranged in the device body; and an external electrode arranged at outside of the device body and being electrically connected to the inner electrode; wherein the external electrode includes: an inner layer covering the device body; an outer layer covering the inner layer and being exposed to the outside; and an intermediate layer arranged between the inner layer and the outer layer, and made of a mixture of a copper metal and a resin, a surface of the copper metal being coated with an oxide film. | 08-28-2014 |
20150014040 | MULTILAYER CERAMIC CAPACITOR AND BOARD FOR MOUNTING OF THE SAME - A multilayer ceramic capacitor may include three external electrodes disposed on a mounting surface of a ceramic body and spaced apart from each other, and first and second lead-out portions extended from a first internal electrode so as to be exposed through the mounting surface of the ceramic body and spaced apart from each other in a length direction of the ceramic body have one or more space portions, respectively, and a board for mounting thereof is provided. | 01-15-2015 |
20150016015 | MULTI-LAYERED CAPACITOR - Disclosed herein is a multi-layered capacitor including: a multi-layered body which includes a capacity part formed by multi-layering a dielectric layer and an internal electrode and a cover part formed by multi-layering the dielectric layer; and a pair of external terminals disposed on both sides of the multi-layered body, in which the cover part is formed by multi-layering a first dielectric layer made of a ferroelectric material and a second dielectric layer made of a paraelectric material, thereby implementing thinness, miniaturization, and high capacity and increasing durability. | 01-15-2015 |
20150016017 | DIELECTRIC COMPOSITION AND MULTI-LAYERED CERAMIC CAPACITOR - A dielectric composition may include a first dielectric powder; and a second dielectric powder having an average grain size smaller than that of the first dielectric powder and included in the dielectric composition in an amount of 0.01 to 1.5 parts by weight based on 100 parts by weight of the first dielectric powder, and a multilayer ceramic capacitor formed using the same. A multilayer ceramic capacitor may include: a ceramic body including dielectric layers; first and second internal electrodes disposed in the ceramic body to face each other with the respective dielectric layers interposed therebetween; and first and second external electrodes electrically connected to the first and second internal electrodes, respectively. The dielectric layers are formed of a dielectric composition including a first dielectric powder and a second dielectric powder having an average grain size smaller than that of the first dielectric powder and included in the dielectric composition in an amount of 0.01 to 1.5 parts by weight based on 100 parts by weight of the first dielectric powder. | 01-15-2015 |
20150016019 | MULTILAYER CERAMIC ELECTRONIC COMPONENT TO BE EMBEDDED IN BOARD - A multilayer ceramic electronic component to be embedded in a board may include: a ceramic body in which a plurality of dielectric layers are stacked; a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, respectively, with at least one of the dielectric layers interposed therebetween; and first and second external electrodes disposed on the end surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. Each of the first and second external electrodes includes a first external electrode layer containing a glass component and disposed on the end surface of the ceramic body and a second external electrode layer being glass-free and covering the first external electrode layer. | 01-15-2015 |
20150043125 | MULTILAYER CERAMIC ELECTRONIC PART, BOARD HAVING THE SAME MOUNTED THEREON, AND MANUFACTURING METHOD THEREOF - A multilayer ceramic electronic part may include: a ceramic body; an active layer including a plurality of first and second internal electrodes disposed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer therebetween; an upper cover layer formed on an upper portion of the active layer; a lower cover layer formed on a lower portion of the active layer and having a thickness thicker than that of the upper cover layer; and first and second external electrodes electrically connected to the first and second internal electrodes, wherein the first and second external electrodes include: first and second conductive layers extended from both end surfaces of the ceramic body onto upper and lower main surfaces thereof; and first and second insulation layers formed on the first and second conductive layers disposed on both end surfaces of the ceramic body. | 02-12-2015 |
20150077898 | MULTILAYER CERAMIC ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME - There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers, a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed to first and second end surfaces of the ceramic body, having the dielectric layer therebetween, first and second electrode layers electrically connected to the first and second internal electrodes, respectively, a conductive resin layer formed on the first and second electrode layers and in regions of the ceramic body adjacent to the first and second electrode layers, and a coating layer formed between a portion of an outer surface of the ceramic body on which the conductive resin layer is to be formed and the conductive resin layer. | 03-19-2015 |
20150096795 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON - A multilayer ceramic capacitor may include: a ceramic body including dielectric layers; first and second internal electrodes disposed in the ceramic body; and first and second external electrodes formed to end surfaces of the ceramic body. The ceramic body may includes an active layer, a capacitance formation portion, and a cover layer, a non-capacitance formation portion, the cover layer includes a plurality of dummy electrode layers. When the number of the first and second internal electrodes is defined as AL, a thickness of each of the first and second internal electrodes is defined as AT, a thickness of each of the dummy electrode layers is defined as DT, and the number of the dummy electrode layers is defined as DL, DL is equal to {(T×x)−(AL×AT)}/DT, x being 9.0% or more. | 04-09-2015 |
20150114701 | MULTILAYER CERAMIC CAPACITOR AND BOARD WITH THE SAME MOUNTED THEREON - A multilayer ceramic capacitor may include a ceramic body including dielectric layers, first and second internal electrodes disposed in the ceramic body to face each other, the dielectric layer being interposed between the first and second internal electrodes, and first and second external electrodes covering both end surfaces of the ceramic body. The ceramic body may include an active layer as a capacitance forming part and a cover layer as a non-capacitive part disposed on at least one surface of upper and lower surfaces of the active layer, the cover layer including at least one buffer layer, and when a thickness of the cover layer is defined as tc, and a thickness of the buffer layer is defined as ti, ti/tc being in a range of 0.15 to 0.90 (0.15≦ti/tc≦0.90). | 04-30-2015 |
20150124372 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND BOARD HAVING THE SAME - A multilayer ceramic electronic component including: a ceramic body having a plurality of dielectric layers stacked therein; active layers including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layers interposed therebetween; and first and second external electrodes formed on the both end surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. The active layers may include a first active layer including a ferroelectric layer and a second active layer including a paraelectric layer, the first and second active layers being alternately stacked. | 05-07-2015 |
20150131199 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND BOARD HAVING THE SAME - A multilayer ceramic electronic component may include a ceramic body having a plurality of dielectric layers stacked in the ceramic body; a plurality of active layers including first and second internal electrodes disposed to be alternately exposed to the end surfaces of the ceramic body with the dielectric layers interposed between the first and second internal electrodes; and dummy layers disposed between the active layers. | 05-14-2015 |
20150221438 | DIELECTRIC COMPOSITION TO BE SINTERED AT LOW TEMPERATURE, MULTILAYER CERAMIC ELECTRONIC COMPONENT CONTAINING THE SAME, AND METHOD OF MANUFACTURING THE MULTILAYER CERAMIC ELECTRONIC COMPONENT - A dielectric composition to be sintered at low temperature may include BaTiO | 08-06-2015 |
20150223340 | MULTILAYER CERAMIC ELECTRONIC COMPONENT TO BE EMBEDDED IN BOARD, MANUFACTURING METHOD THEREOF, AND PRINTED CIRCUIT BOARD HAVING MULTILAYER CERAMIC ELECTRONIC COMPONENT - In a multilayer ceramic electronic component to be embedded in a board, a thickness of a ceramic body in an overall chip may be increased by not allowing an increase in a thickness of an external electrode to occur, while forming a band surface of the external electrode having a predetermined length or greater for connecting the external electrode to an external wiring through a via hole, thereby improving chip strength and preventing the occurrence of damage such as breakage, or the like, a manufacturing method thereof, and a printed circuit board having the multilayer ceramic electronic component. | 08-06-2015 |
20150255213 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND ASSEMBLY BOARD HAVING THE SAME - The present application describes a multilayer ceramic electronic component including a ceramic body having a thickness greater than a width and includes a dielectric layers, and has upper and lower surfaces opposing each other in a thickness direction. First and second side surfaces oppose each other in a width direction, and first and second end surfaces oppose each other in a length direction. First and second internal electrodes are stacked with at least one of the dielectric layers interposed therebetween within the ceramic body in the width direction. A volume increasing part is disposed in a lower portion of the ceramic body in the thickness direction to allow a volume of a lower margin portion of the ceramic body to be greater than that of an upper margin portion thereof. | 09-10-2015 |
20150287533 | MULTILAYER CERAMIC CAPACITOR AND ASSEMBLY BOARD HAVING THE SAME - A multilayer ceramic capacitor may include: a ceramic body having upper and lower surfaces opposing each other in a thickness direction thereof and first and second end surfaces opposing each other in a length direction thereof, a thickness of the ceramic body being greater than a width thereof; a first external electrode disposed on the first end surface to allow a predetermined region of the first end surface adjacent to the upper surface to be exposed; a second external electrode disposed on the second end surface to allow a predetermined region of the second end surface adjacent to the upper surface to be exposed; and first and second internal electrodes disposed within the ceramic body, stacked in a width direction of the ceramic body, and connected to the first and second external electrodes, respectively. | 10-08-2015 |