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Donze, IT

Enzo Donze, S. Giuseppe Jato IT

Patent application numberDescriptionPublished
20100169740ACCELERATING PHASE CHANGE MEMORY WRITES - In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.07-01-2010

Enzo Donze, Agrate Brianza IT

Patent application numberDescriptionPublished
20090080267Generating reference currents compensated for process variation in non-volatile memories - In a current reference generator device, a voltage reference generator stage generates a reference voltage (V03-26-2009
20090196092Programming bit alterable memories - Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.08-06-2009

Enzo M. Donze, Agrate Brianza IT

Patent application numberDescriptionPublished
20090073751Interleaved array architecture - A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.03-19-2009
20090073752Adaptive wordline programming bias of a phase change memory - The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.03-19-2009

Enzo Michele Donze, San Giuseppe Jato IT

Patent application numberDescriptionPublished
20090109738PHASE-CHANGE MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY - A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.04-30-2009
20100165714METHOD OF STORING AN INDICATION OF WHETHER A MEMORY LOCATION IN PHASE CHANGE MEMORY NEEDS PROGRAMMING - A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.07-01-2010
20100165715PROTECTION REGISTER FOR A PHASE-CHANGE MEMORY - A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array.07-01-2010
20100284212METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES - A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.11-11-2010