| Patent application number | Description | Published |
|---|
| 20090021999 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter. | 01-22-2009 |
| 20090201757 | SEMICONDUCTOR DEVICE - Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh. | 08-13-2009 |
| 20100054035 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array | 03-04-2010 |
| 20100090675 | Semiconductor device and test method therefor - Disclosed is a semiconductor device including internal power supply generating circuits for generating internal power supplies and data terminals via which data signals are output or input/output. The internal power supply monitor terminals are in common use with the data terminals. The semiconductor device also includes selection circuits for selecting, by a test control signal, whether or not output voltages of the internal power supply generating circuits are to be output to the data terminals. | 04-15-2010 |
| 20100124139 | SEMICONDUCTOR DEVICE INCLUDING AN ANTI-FUSE ELEMENT - A semiconductor device includes a first high potential power supply, a second low potential power supply, a third power supply having a potential higher than the first, a fourth power supply having a potential more negative than the second, and an anti-fuse element having a node at each end, one of which is connected to the fourth power supply. A driver transistor has a source connected to the third power supply, a gate connected to a control node and a drain connected to one end of the anti-fuse element. A decoding circuit includes a load transistor connected between the third power supply and the control node and at least one selection transistor connected between the second power supply and the control node. A decision circuit is connected to the first and second power supplies. The decision circuit decides the resistance value of the anti-fuse element. The anti-fuse element is rendered electrically conductive in response to activation of the driver transistor as selected by the decoding circuit. The decision circuit decides whether or not the anti-fuse element has been rendered electrically conductive. | 05-20-2010 |
| 20110058401 | Semiconductor memory device having pad electrodes arranged in plural rows - To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area. | 03-10-2011 |
| 20110063927 | Semiconductor device using plural internal operation voltages and data processing system using the same - A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address signal output from the level shifter, address decoders that generate a decode signal by decoding the address signal output from the address controller, and level shifters that convert an amplitude of the address signal or of the decode signal from the second amplitude to the first amplitude such that at least an amplitude level of the decode signal becomes the first amplitude. | 03-17-2011 |
