Patent application number | Description | Published |
20080272948 | CIRCUIT AND METHOD FOR DYNAMICALLY SELECTING CIRCUIT ELEMENTS - Techniques for dynamically selecting circuit elements to combat mismatches are described. In one design, an apparatus includes first, second, and third circuits. The first circuit receives input data and provides first signals that are asserted based on the input data, e.g., with thermometer decoding. The second circuit receives the first signals and provides second signals used to select circuit elements, e.g., current sources, capacitors, resistors, etc. The third circuit generates a control for the second circuit, and the second circuit maps the first signals to the second signals based on this control. In one design, the second circuit includes a set of multiplexers and a control circuit. The multiplexers provides the first signals, circularly rotated by an amount determined by the control, as the second signals. The control circuit accumulates control data (e.g., the input data, pseudo-random data, or a fixed value) with the current control value to obtain new control value. | 11-06-2008 |
20080309537 | PSEUDO-DIFFERENTIAL CLASS-AB DIGITAL-TO-ANALOG CONVERTER WITH CODE DEPENDENT DC CURRENT - A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values. | 12-18-2008 |
20090051431 | HIGH-SWING OPERATIONAL AMPLIFIER OUTPUT STAGE USING ADAPTIVE BIASING - An output stage includes two transistors (switching transistor and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit adjusts the gate voltage on a biasing transistor based on the output node voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings. | 02-26-2009 |
20100237952 | CURRENT CONTROLLED OSCILLATOR WITH REGULATED SYMMETRIC LOADS - An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, V | 09-23-2010 |
20110074615 | WIDEBAND DIGITAL TO ANALOG CONVERTER WITH BUILT-IN LOAD ATTENUATOR - A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage. | 03-31-2011 |
20130076436 | LOAD DETECTING IMPEDANCE MATCHING BUFFER - A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit. | 03-28-2013 |
20140253357 | LOW GLITCH-NOISE DAC - An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2 | 09-11-2014 |
20140266830 | TECHNIQUES TO REDUCE HARMONIC DISTORTIONS OF IMPEDANCE ATTENUATORS FOR LOW-POWER WIDEBAND HIGH-RESOLUTION DACS - A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier. | 09-18-2014 |