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Donghwan
Donghwan Hwang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090276129 | Method and System for Protecting a Starting Clutch - The present invention relates to a method of protecting a starting clutch that generates an estimated equivalent temperature of the starting clutch and performs an operation for protecting the starting clutch if the estimated temperature exceeds critical temperature, in order to prevent the burnout of the starting clutch caused by excessive slip under severe conditions. | 11-05-2009 |
Donghwan Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110063085 | METHOD FOR DETERMINING OPTIMAL FRAME SIZE FOR TAG COLLISION PREVENTION IN RFID SYSTEM - The present invention relates to a method for determining an optimal frame size for tag collision prevention in an Aloha-based RFID system in which frame sizes limited to a certain unit are used to identify tags, the method including the steps of using an RFID for: (a) calculating an estimated optimal frame value for the RFID reader identifying the tags; (b) calculating expected time delays per tag of a left-hand frame size and a right-hand frame size, which show the smallest differences with respect to the estimated optimal frame value, among the frame sizes; (c) comparing, the expected time delay per tag of the left-hand frame size with that of the right-hand frame size; and (d) determining a frame size which has a smaller expected time delay per tag, between the left-hand frame size and the right-hand frame size, to be an optimal frame size. | 03-17-2011 |
Donghwan Lee, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110215851 | DLL INCLUDING 2-PHASE DELAY LINE AND DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF - Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line. | 09-08-2011 |
| 20110221495 | DIGITAL DLL INCLUDING SKEWED GATE TYPE DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF - Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle. | 09-15-2011 |
Donghwan Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110299690 | METHOD AND APPARATUS FOR TRANSMITTING AUDIO DATA - A method and apparatus for transmitting audio data is disclosed. In the method of sending audio data, audio data to be sent are divided into basic channel audio data and supplementary audio data for services of a high channel. When a left channel or a right channel is selected in response to a word selection signal in accordance with the standards of a serial bus, the basic channel audio data corresponding to a selected channel are sent, and at least one of the supplementary audio data is sent during the remaining time until another channel is selected in response to the word selection signal. Accordingly, audio data of a high channel, such as a 5.1 channel, can be sent without a design change using a serial bus for supporting a 2 channel, such as an I2S bus. | 12-08-2011 |