| Patent application number | Description | Published |
|---|
| 20090044039 | Memory system, a memory device, a memory controller and method thereof - The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device. | 02-12-2009 |
| 20090213659 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 08-27-2009 |
| 20100232196 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE PROVIDING ACTIVE TERMINATION CONTROL - A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated. | 09-16-2010 |
| 20110122685 | MULTI-LEVEL PHASE-CHANGE MEMORY DEVICE AND METHOD OF OPERATING SAME - A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages. | 05-26-2011 |
| 20110125982 | MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF CONTROLLING THE MEMORY DEVICE - A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal. | 05-26-2011 |
| 20110126066 | MULTI-CHIP MEMORY SYSTEM AND RELATED DATA TRANSFER METHOD - A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus. | 05-26-2011 |
| 20110134686 | SEMICONDUCTOR DEVICES INCLUDING SENSE AMPLIFIER CONNECTED TO WORD LINE - A semiconductor device includes a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively, and a sense amplifier block for sensing and amplifying a signal of a word line among the plurality of word lines. | 06-09-2011 |
| 20120030414 | NON VOLATILE MEMORY APPARATUS, DATA CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory. | 02-02-2012 |
