| Patent application number | Description | Published |
|---|
| 20080309523 | APPARATUS AND METHOD OF GENERATING DBI SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied. | 12-18-2008 |
| 20100039878 | CIRCUIT AND METHOD FOR GENERATING DATA OUTPUT CONTROL SIGNAL FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The data output control signal generating circuit include sa delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency control multiplexer selects the output enable signal corresponding to column address strobe latency among the plurality of output enable signals, on the basis of the signal obtained by delaying the input signal by the phase difference between the clock and the delay locked loop clock, and outputs the selected signal as the data output control signal. | 02-18-2010 |
| 20100142297 | DATA DRIVER - A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation and a pull-up operation at the same time for a data output terminal during an active interval of a semiconductor memory. The pull-down driver is configured to be activated when the semiconductor memory performs a read operation, and configured to pull down the output terminal in response to a level of an input data. | 06-10-2010 |
| 20100156455 | IMPEDANCE CALIBRATION PERIOD SETTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption. | 06-24-2010 |
| 20100237901 | SEMICONDUCTOR APPARATUS AND DATA OUTPUT METHOD OF THE SAME - A semiconductor apparatus includes a driving control unit configured to receive an enable signal and a data signal. The driving control unit generates a pull-up source signal and a pull-down source signal. The driving control unit is configured to delay the generation timing of the pull-up source signal or the pull-down source signal. The semiconductor apparatus also includes a driver configured to generate a driving data signal by driving the pull-up source signal and the pull-down source signal from the driving control unit. A POD impedance control unit is connected to the output terminal of the driver and has a variable resistance value. | 09-23-2010 |
| 20100238742 | APPARATUS AND METHOD FOR OUTPUTTING DATA OF SEMICONDUCTOR MEMORY APPARATUS - An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended. | 09-23-2010 |
| 20100327962 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a reference voltage generating block, a circuit block, and a transmission line. The reference voltage generating block generates a first reference voltage and generates and outputs a digital code corresponding to the level of the first reference voltage. The circuit block converts the digital code into a second reference voltage and uses the second reference voltage for operation related to the function of the semiconductor integrated circuit. The transmission line is connected between the reference voltage generating block and the circuit block to allow transmission of the digital code to the circuit block. | 12-30-2010 |
| 20110156938 | DATA OUTPUT CIRCUIT - A data output circuit is presented. The data output circuit includes: a data serializer and a driver. The data serializer is configured to generate serial data using first parallel data. The driver is configured to drive the serial data to generate output data. The data serializer is also configured to generate the serial data by multiplexing second parallel data generated by changing a power domain of the first parallel data. | 06-30-2011 |
