Patent application number | Description | Published |
20110058306 | Chip-type electric double layer capacitor and package structure thereof - Disclosed is a package structure of a chip-type electric double layer capacitor which includes a lower package, which houses an electric double layer element and has a package terminal formed thereon to be electrically connected to the electric double layer element, and an upper package which is disposed on a top part of the lower package and seals the electric double layer element from the outside, wherein the package terminals are formed to be protruded from an internal bottom surface and an external bottom surface of the lower package, and the external bottom surface of the lower package has at least two pairs of protrusions formed thereon. | 03-10-2011 |
20110058307 | Chip-type electric double layer capacitor and method for manufacturing the same - The present invention relates to a chip-type electric double layer capacitor and a method for manufacturing a method for manufacturing the same. The chip-type electric double layer capacitor includes an electric double layer element including two electrodes that include two different polarities and electrode terminals protruded on sides opposite to each other, a first separator that prevents the two electrodes from being short-circuited, and a second separator that is disposed at a position opposed to the first separator on the basis of one electrode of the two electrodes; and a package including package terminals attached to the protruded electrode terminals of the two electrodes, which are formed on the bottom thereof and housing the electric double layer element, wherein the electric double layer element is wound on the basis of the protruded electrode terminals opposite to the two electrodes as a reference axis and the electrode terminals are attached to the package terminals, respectively. | 03-10-2011 |
20110085283 | Chip type electric double layer capacitor and method for manufacturing the same - The present invention provides a chip type electric double layer capacitor including: a lower case having an internal space of which an upper surface is opened and an external terminal of which portions exposed to a bottom of the internal space and the outside are connected to each other; an electric double layer capacitor cell disposed in the internal space of the lower case to be electrically connected to the portion of the external terminal, which is exposed to the bottom of the internal space; and an upper cap mounted on the lower case to cover the internal space, and a method for manufacturing the same. | 04-14-2011 |