| Patent application number | Description | Published |
|---|
| 20090001468 | METHOD OF FABRICATING TRANSISTOR INCLUDING BURIED INSULATING LAYER AND TRANSISTOR FABRICATED USING THE SAME - In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively. | 01-01-2009 |
| 20090004800 | Methods of manufacturing semiconductor devices - In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance. | 01-01-2009 |
| 20090057819 | ELECTRICAL FUSE DEVICE - The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link. | 03-05-2009 |
| 20090256214 | Semiconductor device and associated methods - A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region. | 10-15-2009 |
| 20100081246 | Method of manufacturing a semiconductor - A semiconductor device and a method of manufacturing a semiconductor device, the method including forming a gate insulation layer and a gate electrode on a substrate, forming a silicon nitride layer on the gate electrode and the gate insulation layer, partially implanting ions into the silicon nitride layer to convert an upper portion of the silicon nitride layer into a treated silicon layer including the ions, etching the treated silicon layer to form a spacer on a sidewall of the gate electrode, and forming an impurity region in the substrate adjacent to the gate electrode. | 04-01-2010 |
| 20100093166 | Methods of manufacturing a semiconductor device - In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced. | 04-15-2010 |
| 20100167533 | METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer. | 07-01-2010 |
| 20100171182 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING SELECTIVE STRESS RELAXATION OF ETCH STOP LAYER - A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors. | 07-08-2010 |
| 20100200929 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit memory device includes a gate line that extends in a first direction, an active region adjacent to a first end of the gate line and that extends in a second direction, a silicide layer formed on a top surface of the active region, on a top surface of the gate line, on both sidewalls of the first end of the gate line, and on a transverse endwall of the first end of the gate line. A spacer may be formed on sidewalls of the gate line, excluding the first end of the gate line, and a contact shared by the active region may be formed on the first end of the gate line. | 08-12-2010 |
| 20100207210 | Semiconductor devices - A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern. | 08-19-2010 |
| 20110018044 | ETCH STOP LAYERS AND METHODS OF FORMING THE SAME - A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress. | 01-27-2011 |
| 20110136311 | SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device. | 06-09-2011 |
