Patent application number | Description | Published |
20080280391 | METHODS OF MANUFACTURING MOS TRANSISTORS WITH STRAINED CHANNEL REGIONS - In some methods of manufacturing transistors, a gate electrode and a gate insulation layer pattern are stacked on a substrate. Impurity regions are formed at portions of the substrate that are adjacent to the gate electrode by implanting Group III impurities into the portions of the substrate. A diffusion preventing layer is formed on the substrate and covering the gate electrode. A nitride layer is formed on the diffusion preventing layer. The substrate is thermally treated to form a strained silicon region in the substrate between the impurity regions and to activate the impurities in the impurity regions. A high performance PMOS transistor and/or CMOS transistor may thereby be manufactured on the substrate. | 11-13-2008 |
20080290446 | SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING WET ETCH BARRIERS AND METHODS OF FABRICATING SAME - A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed. | 11-27-2008 |
20090020845 | SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING DOPED OXIDE FILM LINERS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed. | 01-22-2009 |
20090032881 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME IN WHICH A MOBILITY CHANGE OF THE MAJOR CARRIER IS INDUCED THROUGH STRESS APPLIED TO THE CHANNEL - A semiconductor device includes a semiconductor substrate, a gate structure formed on the semiconductor substrate, wherein the gate structure includes a gate electrode formed on the semiconductor substrate and spacers formed on sidewalls of the gate electrode, source/drain regions formed in the semiconductor substrate on both sides of the gate structure, and an etch stop layer, which is formed on the gate structure, and includes a first region formed on the spacers and a second region formed on the gate electrode, wherein the thickness of the first region is about 85% that of the thickness of the second region or less. | 02-05-2009 |
20090104741 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING A PLASMA PROCESS WITH NON-SILANE GAS INCLUDING DEUTERIUM - Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer. | 04-23-2009 |
20090283764 | TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME - Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer. | 11-19-2009 |
20100109729 | DUTY DETECTING CIRCUIT AND DUTY CYCLE CORRECTOR INCLUDING THE SAME - A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code. | 05-06-2010 |
20100164573 | SEMICONDUCTOR DEVICE - A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit. | 07-01-2010 |
20100167474 | Methods of Forming Semiconductor-On-Insulating (SOI) Field Effect Transistors with Body Contacts - Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region. | 07-01-2010 |
20110163386 | Semiconductor Devices Including Dehydrogenated Interlayer Dielectric Layers - Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided. | 07-07-2011 |
20110267118 | DELAY LOCKED LOOP OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay locked loop (DLL) of a semiconductor integrated circuit includes a first delay line configured to variably delay a source clock signal and output a locked clock signal, a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal, a second delay line configured to variably delay the locked clock signal, a first delay controller configured to control the first delay time of the first delay line, a second delay controller configured to control the minimum delay time of the second delay line, and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on locking state of the delay lines. | 11-03-2011 |
20110291725 | DUTY DETECTION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT INCLUDING THE SAME - A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock. | 12-01-2011 |
20110318890 | METHODS OF FORMING SEMICONDUCTOR-ON-INSULATING (SOI) FIELD EFFECT TRANSISTORS WITH BODY CONTACTS - Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region. | 12-29-2011 |
20130169337 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 07-04-2013 |
20140103987 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 04-17-2014 |
20140152360 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 06-05-2014 |