| Patent application number | Description | Published |
|---|
| 20080199975 | METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern. | 08-21-2008 |
| 20080203456 | Dynamic random access memory devices and methods of forming the same - Dynamic random access memory (DRAM) devices include first node pads and second node pads alternately arranged in a first direction on a substrate to form a first pad column. A width of the second node pads in a second direction, perpendicular to the first direction, is greater than a width of the first node pads in the second direction. Storage electrodes are electrically connected to the first node pads and the second node pads. Bit line pads may be arranged in the first direction on the substrate to form a second pad column. The second pad column is adjacent the first pad column and displaced therefrom in the second direction. | 08-28-2008 |
| 20080283957 | Method of Fabricating Semiconductor Device Having Self-Aligned Contact Plug and Related Device - Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided. | 11-20-2008 |
| 20080284029 | Contact structures and semiconductor devices including the same and methods of forming the same - Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes. | 11-20-2008 |
| 20090008701 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a charge trap layer formed on the semiconductor substrate, a blocking layer formed on the charge trap layer, and a gate electrode formed on the blocking layer. Sides of blocking layer extend laterally beyond sides of the charge trap layer and lateral sides of the gate electrode. | 01-08-2009 |
| 20090155968 | METHOD OF FORMING A DIELECTRIC LAYER PATTERN AND METHOD OF MANUFACTURING A NON-VOLATILE MEMORY DEVICE USING THE SAME - In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed. | 06-18-2009 |
| 20090193721 | ABRASIVE PARTICLES, METHOD OF MANUFACTURING THE ABRASIVE PARTICLES, AND METHOD OF MANUFACTURING CHEMICAL MECHANICAL POLISHING SLURRY - Disclosed are abrasive particles, a method for manufacturing the abrasive particles, and a method for manufacturing a Chemical Mechanical Polishing (CMP) slurry. The method for manufacturing abrasive particles for the CMP slurry includes preparing a raw material precursor, drying the raw material precursor, and calcining the dried raw material precursor using a calcination furnace where a gas atmosphere having relatively less oxygen in comparison with an air atmosphere is created. | 08-06-2009 |
| 20090261405 | Non-Volatile Memory Devices - Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern. | 10-22-2009 |
| 20100193966 | Contact Structures and Semiconductor Devices Including the Same - Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are is etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes. | 08-05-2010 |
| 20100297840 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process. | 11-25-2010 |
| 20110152318 | NOVEL COMPOUNDS, ISOMER THEREOF, OR PHARMACEUTICALLY ACCEPTABLE SALTS THEREOF AS VANILLOID RECEPTOR ANTAGONIST AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME - This present invention relates to novel compounds, isomer thereof or pharmaceutically acceptable salts thereof as vanilloid receptor (Vanilloid Receptor 1; VR1; TRPV1) antagonist; and a pharmaceutical composition containing the same. The present invention provides a pharmaceutical composition for preventing or treating a disease such as pain, migraine, arthralgia, neuralgia, neuropathies, nerve injury, skin disorder, urinary bladder hypersensitiveness, irritable bowel syndrome, fecal urgency, a respiratory disorder, irritation of skin, eye or mucous membrane, stomach-duodenal ulcer, inflammatory diseases, ear disease, heart disease and so on. | 06-23-2011 |
