| Patent application number | Description | Published |
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| 20100112774 | Variable Resistance Memory Device and Methods of Forming the Same - A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern. | 05-06-2010 |
| 20100227457 | Method of forming phase change material layer and method of fabricating phase change memory device - A method of forming a phase change material layer and a method of fabricating a phase change memory device, the method of forming a phase change material layer including forming an amorphous germanium layer by supplying a germanium containing first source into a reaction chamber; cutting off supplying the first source after forming the amorphous germanium layer; and forming amorphous Ge | 09-09-2010 |
| 20100248442 | METHODS OF FORMING A PHASE CHANGE MEMORY DEVICE - Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell. | 09-30-2010 |
| 20100248460 | Method of forming information storage pattern - A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination. | 09-30-2010 |
| 20110032752 | Multi-Level Memory Device Using Resistance Material - A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC. | 02-10-2011 |
| 20110032753 | MEMORY CELLS INCLUDING RESISTANCE VARIABLE MATERIAL PATTERNS OF DIFFERENT COMPOSITIONS - A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns. | 02-10-2011 |
| Patent application number | Description | Published |
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| 20090035877 | METHODS OF FORMING A FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A FERROELECTRIC CAPACITOR INCLUDING THE SAME - A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains. | 02-05-2009 |
| 20090061538 | Methods of forming ferroelectric capacitors and methods of manufacturing semiconductor devices using the same - In a method of forming a ferroelectric capacitor, a lower electrode layer is formed on a substrate. A first crystalline layer is formed on the lower electrode layer. A ferroelectric layer is formed on the first crystalline layer. The first crystalline layer one of prevents a component of the ferroelectric layer from diffusing into the lower electrode layer and mitigates fatigue of the ferroelectric layer. An upper electrode layer is formed on the ferroelectric layer. | 03-05-2009 |
| 20090130797 | METHODS OF FORMING PHASE-CHANGEABLE MEMORY DEVICES USING GROWTH-ENHANCING AND GROWTH-INHIBITING LAYERS FOR PHASE-CHANGEABLE MATERIALS - Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer. | 05-21-2009 |
| 20090233421 | Methods of Fabricating Semiconductor Device Including Phase Change Layer - Provided are methods of fabricating a semiconductor device including a phase change layer. Methods may include forming a dielectric layer on a substrate, forming an opening in the dielectric layer and depositing, on the substrate having the opening, a phase change layer that contains an element that lowers a process temperature of a thermal treatment process to a temperature that is lower than a melting point of the phase change layer. Methods may include migrating a portion of the phase change layer from outside the opening, into the opening by the thermal treatment process that includes the process temperature that is lower than the melting point of the phase change layer. | 09-17-2009 |
| 20090280599 | PHASE CHANGE MEMORY DEVICE AND METHOD OF FABRICATION - A phase change memory device includes a bottom electrode on a substrate, a phase change material pattern on the bottom electrode, and a top electrode on the phase change material pattern. The phase change material pattern includes at least 50 percent antimony (Sb). | 11-12-2009 |
