| Patent application number | Description | Published |
|---|
| 20090106503 | Method, device, and system for preventing refresh starvation in shared memory bank - A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register. | 04-23-2009 |
| 20090296510 | Semiconductor memory device having refresh circuit and word line activating method therefor - A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block. | 12-03-2009 |
| 20100124138 | Semiconductor memory device having variable-mode refresh operation - A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array having a plurality of memory banks, the memory banks including word lines and a plurality of memory cells, and a word line activation control unit that performs a control to access data corresponding to an externally same address in at least two memory cells by simultaneously activating a predetermined number of word lines from among the word lines sharing the bit line sense amplifier, and the word line activation control unit operates in response to a determination mode allowing signal that is set in accordance with a used memory density. | 05-20-2010 |
| 20100177576 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated. | 07-15-2010 |
| 20100316299 | METHOD AND APPARATUS FOR DETERMINING PRESENCE OF USER'S HAND TREMOR OR INTENTIONAL MOTION - A method is provided for determining presence of a user's hand tremor or intentional motion during recognition of an image through photographing. Image sample blocks of a previous frame are detected by using an edge detecting method. A block distance between the detected image sample block of the previous frame and an estimated image sample block of a current frame is calculated. The calculated block distance is compared with a first threshold. The calculated block distance is compared with a second threshold when the calculated block distance is less than the first threshold. | 12-16-2010 |
| 20110013807 | APPARATUS AND METHOD FOR RECOGNIZING SUBJECT MOTION USING A CAMERA - A method for recognizing a subject motion using a camera is provided, in which each of the previous and current image frames received from the camera is split into multiple image blocks, motion blocks are detected among the image blocks based on a difference between previous and current pixel values for each of the image frames, a motion center is detected based on positions of the motion blocks for each image frame, and the subject motion appearing in the previous and current image frames is recognized based on the motion centers of the previous and current image frames. | 01-20-2011 |
| 20110069572 | ROW ADDRESS CODE SELECTION BASED ON LOCATIONS OF SUBSTANDARD MEMORY CELLS - A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together. | 03-24-2011 |
| 20110072205 | MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell. | 03-24-2011 |
| 20110093235 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip. | 04-21-2011 |
| 20110107006 | Multiprocessor system and method thereof - A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port. | 05-05-2011 |
| 20110116335 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block. | 05-19-2011 |
