Dong-Hyuk
Dong Hyuk Chae, Hwasung-City KR
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20130329497 | METHOD AND APPARATUS FOR MANAGING OPEN BLOCKS IN NONVOLATILE MEMORY DEVICE - A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy. | 12-12-2013 |
Dong Hyuk Chang, Goyang-Si KR
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20130164046 | DOCTOR BLADE FOR IMAGE FORMING DEVICE - A doctor blade of an image forming device for controlling a thickness of a toner coated on a development roller to a uniform thickness inside the image forming device is disclosed. The doctor blade includes: a support rod serving as a support fixture; a plate formed in an L shape, the plate being mounted on the lower surface and the rear surface of the support rod in contact with them to thereby serve to keep a uniform thickness of the toner in a state where the bottom surface is in contact with the development roller, the plate including a base layer of a metallic material and a coated layer formed on the bottom surface of the base layer getting in contact with the development roller; and a torsion spring mounted above the support rod to pressurize the support rod and the plate in order to fix the support rod and the plate. The doctor blade is reusable because only the plate is simply replaced with a new one when the coated layer formed on the plate is worn out. | 06-27-2013 |
Dong Hyuk Jang, Seoul KR
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20080298650 | Optical finger print acquisition apparatus using a prism - An optical fingerprint acquisition apparatus using a prism, which can improve the quality of a fingerprint image acquired by an image sensor, is provided. The optical fingerprint acquisition apparatus using the prism includes a pentagon prism including an input face | 12-04-2008 |
20110188189 | FLEXIBLE ELECTRONIC PRODUCT HAVING A SHAPE CHANGE CHARACTERISTIC AND METHOD THEREOF - A flexible electronic product includes a flexible electronic assembled body and an actuator including a shape memory member. The actuator of the flexible electronic product deforms in response to an input. The flexible electronic assembled body includes a flexible display device, such as an organic light emitting diode (OLED), a plastic liquid crystal display (LCD), a plastic plasma display panel (PDP), an electronic ink panel, an organic thin film transistor (OTFT). | 08-04-2011 |
20140029847 | IMAGE ELEMENT BRIGHTNESS ADJUSTMENT - One or more techniques and/or systems are disclosed for adjusting a brightness level of an image element representing an image of a body-part relief print. A first weighting factor can be determined for a first image element that may be comprised in an initial image captured by a body-part relief print image capture device. A body-part relief print weighting value can be determined, which can be based at least upon a combination of the first weighting factor and a second image element brightness value for a second image element that may be comprised in a body-part relief print image, which may be captured by a same body-part relief print image capture device as the initial image. An adjusted brightness level can be determined for the second image element, based at least upon a combination of the body-part relief print weighting value and the second image element brightness value. | 01-30-2014 |
20150294099 | BIOMETRIC SENSOR FOR TOUCH-ENABLED DEVICE - One or more techniques and/or systems are disclosed for a biometric imager that can be integrated into a touch enabled computing device, and may be used to interact with the device. Upon touching the touch-enabled surface of the device, an image of at least a portion of the touch object can be captured and used in conjunction with identification of the user and/or for input to the device. The systems or techniques, described herein, may be integrated into a portion of the surface of such a device, and may comprise a luminescent layer that can emit photons upon touch, and an image capture component that can generate data indicative of an image of at least a portion of the touch object. | 10-15-2015 |
Dong Hyuk Jeon, Daejeon KR
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20120153223 | ABSORBENT FOR CAPTURING CARDON DIOXIDE INCLUDING AMINO ACID HAVING MULTI AMINE GROUPS AND METAL HYDROXIDE - Provided is an absorbent for capturing carbon dioxide. The absorbent may include an amino acid with multiple amine groups and an alkali-metal hydroxide mixed with the amino acid and thus, may increase an absorption capacity for carbon dioxide. When a sterically hindered effect is induced to the amino acid with multiple amine groups, the absorption capacity for carbon dioxide may increase and heat of absorption reaction may decrease and thus, energy consumed for regeneration of an absorbent may be reduced. The absorbent for capturing carbon dioxide may include amino acid with multiple amine groups and the metal hydroxide, and may provide a functional group around the amine groups to cause an sterically hindered effect and thus, the absorption capacity for carbon dioxide and an carbon dioxide absorption rate may increase, and the capital cost for a carbon dioxide capturing process and an operating cost may be significantly reduced. | 06-21-2012 |
Dong Hyuk Jeong, Gyeonggi-Do KR
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20160082886 | APPARATUS FOR ASSISTING BACKWARD DRIVING AND METHOD THEREOF - An apparatus for assisting backward driving of a vehicle includes: a geography detecting sensor be mounted at a rear of the vehicle and configured to obtain rear geographic information; an image sensor configured to obtain an rear image of the vehicle; a backward path calculator configured to calculate a backward path based on the rear geographic information; an image synthesizer configured to synthesize a guideline with the rear image based on the backward path; and a display configured to display the synthesized image. The backward path is calculated to terminate at a limit point rear of the vehicle where it is determined that there is an impeded driving area. | 03-24-2016 |
Dong Hyuk Joo, Seoul KR
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20150207051 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a stacked semiconductor structure including a first conductivity-type semiconductor layer having a top surface divided into a first region and a second region, and an active layer and a second conductivity-type semiconductor layer disposed sequentially on the second region of the first conductivity-type semiconductor layer. First and second contact electrodes are disposed in the first region of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, respectively. A current spreading layer is disposed on the second contact electrode and comprises a first conductive layer having a first resistivity and a second conductive layer having a second resistivity smaller than the first resistivity alternately stacked. | 07-23-2015 |
Dong Hyuk Kim, Gyeonggi-Do KR
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20110271548 | HYBRID DRYING SYSTEM AND METHOD FOR CONTROLLING A HYBRID DRYING SYSTEM - Disclosed is a hybrid drying system where a cold-air drier and a desiccant drier are combined to increase drying efficiency (extent of dehumidification/power consumption), thereby shortening drying time and significantly reducing operation costs. The hybrid drying system includes a desiccant drier installed between an evaporator and a condenser and having an absorbing part configured to produce dry air from the cold-air dried air which has passed through the evaporator and a detaching part configured to supply recycled air heated by the condensation heat of the condenser as a recycling heat source ; a heat exchanger configured to heat-exchange exterior air with recycled exhaust air with the recycled air to retrieve exhaust heat; and a control unit configured to simultaneously control a cold-air drying operation and a desiccant drying operation according to the humidity and temperature of the drying chamber. The hybrid drying system is operated through a freezing cycle, a drying cycle, a drying chamber circulating cycle, and a recycling cycle. | 11-10-2011 |
Dong Hyuk Kim, Seongnam-Si KR
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20100300123 | HYBRID DESICCANT DEHUMIDIFYING APPARATUS AND CONTROL METHOD THEREOF - Disclosed are a hybrid desiccant dehumidifying apparatus and a control method thereof which are employed under poor environment, such as a ship painting field. External air cooled by an evaporator is dehumidified and heated while passing through a desiccant dehumidifier and external air heated by condensation heat of a condenser is supplied to the desiccant dehumidifier as a regeneration air source such that high-temperature and high-humidity regeneration. A cooler is integrally formed with the desiccant dehumidifier so that the hybrid desiccant dehumidifying apparatus is manufactured in a compact size and the operating cost thereof is significantly reduced. | 12-02-2010 |
20110201166 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face. | 08-18-2011 |
20110230027 | Methods of Forming Semiconductor Devices Having Faceted Semiconductor Patterns - Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate. | 09-22-2011 |
20110241071 | Semiconductor Devices Having Field Effect Transistors With Epitaxial Patterns in Recessed Regions - A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region. | 10-06-2011 |
20120021537 | METHODS OF EVALUATING EPITAXIAL GROWTH AND METHODS OF FORMING AN EPITAXIAL LAYER - A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio. | 01-26-2012 |
20120223364 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer. | 09-06-2012 |
20120241815 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 09-27-2012 |
20120244674 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip. | 09-27-2012 |
20130109144 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME | 05-02-2013 |
20140084350 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface. | 03-27-2014 |
20140087537 | SEMICONDUCTOR DEVICES INCLUDING MULTILAYER SOURCE/DRAIN STRESSORS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern. | 03-27-2014 |
20140312430 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 10-23-2014 |
20150140747 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface. | 05-21-2015 |
20150145072 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer. | 05-28-2015 |
20150179795 | SEMICONDUCTOR DEVICES INCLUDING MULTILAYER SOURCE/DRAIN STRESSORS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern. | 06-25-2015 |
20150214051 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer. | 07-30-2015 |
20150221654 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers. | 08-06-2015 |
20150349122 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 12-03-2015 |
20160049512 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 02-18-2016 |
Dong Hyuk Kim, Paju-Si KR
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20150187750 | ANTISTATIC DEVICE OF DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Discussed are an antistatic device of a display device, which has a high electrostatic discharge (ESD) speed and reduces consumption power, and a method of manufacturing the same. The antistatic device can include a first switching thin film transistor (TFT) in which an active layer is formed of oxide, a second switching TFT in which an active layer is formed of oxide, and an equalizer TFT in which an active layer is formed of amorphous silicon. | 07-02-2015 |
Dong Hyuk Lee, Cheongju-Si KR
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20150190203 | SURGICAL GRASPER FOR MEASURING FORCE - The present invention relates to a surgical grasper for measuring force, the surgical grasper having a first gripping part and a second gripping part, the first gripping part being provided with a first recess portion recessed inwardly from an outer surface of the first gripping part, the surgical grasper including: a first elastic dielectric body having one surface surface-contacting the first recess portion; an electrode part including a pair of electrodes opposed to each other on opposite surfaces of the first elastic dielectric body and having a distance between the electrodes, varied by external force applied thereto; and a first finishing part surface-contacting the other surface of the first elastic dielectric body and formed to correspond to the first recess portion to thereby be inserted into the first recess portion. | 07-09-2015 |
20150292969 | CAPACITIVE TYPE 6-AXIAL FORCE/TORQUE SENSOR - A capacitive type sensor includes a circuit board, electrodes formed on a first surface of the circuit board, and an electrode plate disposed above the circuit board, wherein the electrodes comprise pairs of electrodes disposed from a distance from a center of the circuit board, and the pairs of electrodes being spaced apart from each other. | 10-15-2015 |
Dong Hyuk Lee, Gimpo-Si KR
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20090005836 | Cochlear Implant - There is provided a cochlear implant for improving the hearing ability of a patient suffered from hearing impairment comprising an internal receiving unit implanted into the body, which comprises a receiving part for receiving external signal, an active electrode and a reference electrode, characterized in that the active electrode is constructed with a single electrode wire having different thickness in at least two different regions. The active electrode of the internal receiving unit is inserted into a space formed at between the mastoid bone and the ear canal skin and end of the active electrode is inserted into the scala tympani of the cochlea and directly stimulates spiral ganglion. The cochlear implant provides easier implantation into the body and improved hearing ability at a lower cost. | 01-01-2009 |
Dong Hyuk Lee, Gyeonggi-Do KR
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20120089513 | NEAR FIELD COMMUNICATION TERMINAL CAPABLE OF LOADING CARD WITH MONEY AND METHOD OF OPERATING THE SAME - Disclosed herein are an NFC terminal and a method of operating an NFC terminal. The NFC terminal includes an NFC unit and a payment unit. The NFC unit communicates with an external payment processing server. The payment unit pays for loaded money data while communicating with the payment processing server. | 04-12-2012 |
Dong Hyuk Nam, Seoul KR
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20110015407 | METHOD FOR THE PREPARATION OF ATORVASTATIN AND INTERMEDIATES USED THEREIN - The present invention relates to a novel method for preparing atorvastatin. According to the present invention, provided are a novel intermediate of the preparation of atorvastatin and a method of preparing large amounts of atorvastatin in a safe manner using the intermediate. | 01-20-2011 |
Dong Hyuk Oh, Seoul KR
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20150134246 | MULTI-PATH ROUTING TELEMATICS SYSTEM AND METHOD - A multi-path routing telematics system and method are provided. The method includes receiving, by a controller, a route request from a navigation device and connecting to one or more route-providing servers based on corresponding plug-ins. In addition, the controller is configured to collect routes and transmit them to the navigation device. The route-providing servers are each configured to create a route pursuant to the route request. | 05-14-2015 |
Dong Hyuk Shin, Yongin-Si KR
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20090309889 | Method and Apparatus for Contolling Writing of Data to Graphic Memory - A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space. | 12-17-2009 |
20130278618 | Method and Apparatus for Controlling Writing of Data to Graphic Memory - A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space. | 10-24-2013 |
20150022540 | METHOD AND APPARATUS FOR CONTROLLING WRITING OF DATA TO GRAPHIC MEMORY - A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space. | 01-22-2015 |
Dong Hyuk Shin, Gyeonggi-Do KR
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20090176846 | N-hydroxy-4- {5- [4- (5-isopropyl-2-methyl-1, 3-thiazol-4-yl) phenoxy] pentoxy} benzamidine 2 methanesulfonic acid salt - Disclosed is an N-Hydroxy-4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxy]pentoxy} benzamidine 2 methansulfonic acid salt, which has excellent bioavailability. Also disclosed are a method of preparing the compound and a pharmaceutical composition comprising the compound. | 07-09-2009 |
20100317853 | NOVEL IMATINIB CAMSYLATE AND METHOD FOR PREPARING THEREOF - The present invention relates to a novel imatinib camsylate and a method for preparing the same. Imatinib camsylate according to the present invention has a faster absorption rate and higher absorption concentration in terms of pharmacokinetics, and further has excellent water solubility, as compared to commercially available imatinib mesylate. | 12-16-2010 |
Dong Hyuk Woo, Campbell, CA US
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20140181477 | Compressing Execution Cycles For Divergent Execution In A Single Instruction Multiple Data (SIMD) Processor - In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed. | 06-26-2014 |
20150095542 | COLLECTIVE COMMUNICATIONS APPARATUS AND METHOD FOR PARALLEL SYSTEMS - A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs. | 04-02-2015 |
20150242210 | Monitoring Vector Lane Duty Cycle For Dynamic Optimization - In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed. | 08-27-2015 |
Dong-Hyuk Han, Seoul KR
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20110142159 | METHOD AND APPARATUS FOR HYBRID VIRTUAL MIMO TRANSMISSION IN WIRELESS AD-HOC NETWORK - A hybrid virtual multiple-input multiple-output (V-MIMO) transmission method of a management node in a wireless ad-hoc network in which a transmission path from a source node to a destination node is divided into one or more sections is provided. The hybrid V-MIMO transmission method includes obtaining one or more pieces of node information of one or more nodes by transmitting an information request message to the nodes in response to a transmission request message for data transmission from the source node to the destination node; setting a shortest path (SP) from the source node to the destination node based on the obtained node information; determining transmission schemes individually for nodes present on the SP; issuing a transmission preparation request by transmitting the determined transmission schemes to the respective corresponding nodes; and transmitting a transmission start message to the source node in response to transmission ready responses from the respective nodes. | 06-16-2011 |
Dong-Hyuk Heo, Chungcheongbuk-Do KR
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20150247626 | OLED LIGHTING MODULE - The present invention discloses a lighting module using an organic light emitting device (OLED) and particularly, a lighting module using the OLED which stably couples a power supply terminal to an electrode pad which is formed on a glass substrate of an OLED illumination plate. | 09-03-2015 |
Dong-Hyuk Kim, Seongma-Si KR
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20130161751 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS - A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer. | 06-27-2013 |
Dong-Hyuk Kim, Suwon-Si KR
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20110104838 | LIQUID CRYSTAL DISPLAY AND METHOD OF MAKING THE SAME - A method of making a liquid crystal display having a display region and a non-display region, the method comprises forming a thin film transistor (“TFT”) having a drain electrode on an insulating substrate, forming an inorganic layer and an organic insulating layer sequentially on the TFT, forming an organic insulating layer pattern, by patterning the organic insulating layer, comprising a first organic layer hole to expose the inorganic layer on the drain electrode and a second organic layer hole formed along a circumference of the display region where the organic insulating layer is partially removed, removing the inorganic layer exposed through the first organic layer hole and the organic insulating layer remaining in the second organic layer hole, and forming a sealant in the second organic hole. The present invention thus provides a method of making an LCD to prevent a color filter substrate separating from a TFT substrate using fewer masks. | 05-05-2011 |
Dong-Hyuk Kim, Yongin-Si KR
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20140027828 | X-RAY DETECTOR - An X-ray detector including: a substrate that is divided into a light detection area and a non-detection area and includes a plurality of pixels; a photodiode disposed on the light detection area; a thin film transistor that is disposed on the non-detection area and is electrically connected to a lower portion of the photodiode; a plurality of wires that are electrically connected to the thin film transistor and are positioned on the non-detection area; at least one insulating layer disposed so as to cover at least the thin film transistor and the plurality of wires; a scintillator layer disposed on the at least one insulating layer over an entire surface of the substrate; and a shielding part disposed between the at least one insulating layer and the scintillator layer to shield the non-detection area. | 01-30-2014 |
Dong-Hyuk Kim, Seoul KR
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20140124766 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes first and second electrodes facing each other on a substrate, at least one emission layer formed between the first and second electrodes, a hole transport layer formed between the first electrode and the emission layer, and an electron transport layer formed between the second electrode and the emission layer, wherein the emission layer includes a first emission mixed layer formed on the hole transport layer, the first emission mixed layer including a first hole-type host and a first phosphorescent dopant, and a second emission mixed layer formed between the first emission mixed layer and the electron transport layer, the second emission mixed layer including a first electron-type host and a second phosphorescent dopant. | 05-08-2014 |
20150188095 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device includes a first substrate including a display area, wherein a plurality of pixels each including sub-pixels is defined in the display area; a switching thin film transistor and a driving thin film transistor in each of the sub-pixels over the first substrate; light-blocking patterns in at least one of the sub-pixels; a color filter layer in at least one sub pixel; a first passivation layer over the switching thin film transistor, the driving thin film transistor and the light-blocking patterns; a first electrode in each of the sub-pixels over the first passivation layer; an organic light emitting layer on the first electrode all over the display area; and a second electrode on the organic light emitting layer all over the display area. | 07-02-2015 |
20150287463 | NONVOLATILE MEMORY DEVICE HAVING PAGE BUFFER UNITS UNDER A CELL - A nonvolatile memory device includes a cell array, a distributed page buffer including a plurality of page buffer units disposed below the cell array, the plurality of page buffer units having a certain size; and a distributed page buffer control circuit including a plurality of page buffer control circuit units, each page buffer control circuit unit being arranged at one side of a corresponding page buffer unit, and configured to control operations of the corresponding page buffer unit, the plurality of page buffer control circuit units each having a predetermined size. | 10-08-2015 |
20150311462 | WHITE ORGANIC LIGHT EMITTING DEVICE - Disclosed is a white organic light emitting device in which a lifetime of a device is enhanced. The white organic light emitting device includes a first emission part between a first electrode and a second electrode and a second emission part on the first emission part. At least one among the first and second emission parts includes an emission area control layer. The white organic light emitting device includes a first emission part between a first electrode and a second electrode, a second emission part on the first emission part, and a third emission part on the second emission part. At least one among the first to third emission parts includes an emission area control layer. | 10-29-2015 |
Dong-Hyuk Kim, Taebaek-Si KR
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20140363582 | METHOD OF PREPARING YTTRIA SOLUTION FOR BUFFER LAYER OF SUBSTRATE - Disclosed herein is a method of preparing a yttria solution for a buffer layer of a substrate, including the steps of: (a) mixing yttrium acetate tetrahydrate with methanol to form a mixture and then stirring the mixture; (b) injecting diethanolamine as a chelating agent into the mixture of the step (a) and then stirring the mixture to synthesize a composite; and (c) filtering the composite synthesized in the step (b) using a filter to obtain a sol. The method is advantageous in that the yttria solution prepared in this method is applied onto a substrate to flatten the substrate, and is used to form a diffusion barrier serving as a buffer layer for preventing the diffusion of a substrate material. | 12-11-2014 |
20150248952 | HIGH-TEMPERATURE SUPERCONDUCTING WIRE MATERIAL - A high-temperature superconducting wire material comprising: a pre-superconducting wire material layer formed by forcibly removing a metal substrate from a superconducting wire material formed by including the metal substrate, a buffer layer formed on the upper surface of the metal substrate and a superconducting conductive layer formed on the upper surface of the buffer layer; a silver (Ag) protective layer formed on the lower surface of the pre-superconducting wire material layer; and a copper (Cu) protective layer formed on the lower surface of the Ag protective layer. Since a superconducting wire material is formed by stripping a metal substrate of a second-generation high-temperature superconducting wire material and forming a metal protective layer, advantages include the reduction of a magnetization loss due to the magnetism of the substrate, excellent stability of the wire material, and increases in Je (engineering current density) due to the minimization of the thickness of the superconducting wire material. | 09-03-2015 |
Dong-Hyuk Kim, Gwanak-Gu KR
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20150097161 | ORGANIC LIGHT EMITTING DEVICE AND ORGANIC LIGHT EMITTING DISPLAY HAVING THE SAME - Disclosed is an organic light emitting device including a first electrode, a second electrode, and an organic laminate formed between the first and second electrodes. The organic laminate includes, a multilayer-light emitting structure that includes two or more light emitting layers emitting light of different colors and a charge transport control layer formed at boundaries between the two or more light emitting layers and controlling the amount of charges transported between the two or more light emitting layer. A first light emitting layer of the two or more light emitting layers is between a hole transport layer and the charge transport control layer and formed of a mixture including a first dopant and a host of a hole transport material. Both a hole transport layer and the charge transport control layer are formed of the same material as the host of the first light emitting layer. | 04-09-2015 |
Dong-Hyuk Kim, Incheon KR
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20150253073 | RE-LIQUEFYING METHOD FOR STORED LIQUID - Provided is a re-liquefying method for a stored liquid which has a simple structure or operation and excellent process efficiency. Since the method does not use separate refrigerant, the structure or operation in the re-liquefying method is significantly simplified. In addition, since a portion of a main stream is separated to form a cycle similar to a refrigerant cycle which cools the mainstream, the process efficiency of the re-liquefying method is significantly improved. | 09-10-2015 |
Dong-Hyuk Kim, Hwaseong-Si KR
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20160061966 | X-RAY IMAGING APPARATUS AND CONTROL METHOD THEREOF - Disclosed herein is an X-ray imaging apparatus including: a gate driver configured to apply a turn-on signal to a plurality of gate lines; and a readout circuit configured to read out a signal from the plurality of gate lines, wherein if an X-ray signal is detected from a gate line of the plurality of gate lines, the gate driver changes a turn-on time period of the turn-on signal. | 03-03-2016 |
Dong-Hyuk Lee US
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20120126840 | Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment - A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes. | 05-24-2012 |
Dong-Hyuk Lee, Suwon-Si KR
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20110202918 | VIRTUALIZATION APPARATUS FOR PROVIDING A TRANSACTIONAL INPUT/OUTPUT INTERFACE - A virtualization apparatus and method for providing a transactional input/output interface to prevent input/output performance from deteriorating are provided. The virtualization apparatus includes hardware, a virtual machine monitor to support a plurality of operating systems to use the hardware, and a transaction device driver that executes transactions for hardware I/O operation and to provide an interface for executing a transaction for input/output operations to/from the hardware. | 08-18-2011 |
Dong-Hyuk Lim, Seoul KR
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20090313410 | BI-DIRECTIONAL MULTI-DROP BUS MEMORY SYSTEM - A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs. | 12-17-2009 |
20140017451 | ADHESIVE, ADHESIVE TAPE, AND DISPLAY DEVICE - An adhesive includes an acrylic copolymer synthesized from a composition including a solution polymerizable acryl-based monomer, a vinyl-based monomer that is copolymerizable with the solution polymerizable acryl-based monomer, a β-carboxylethyl acrylate monomer, and a reaction initiator, and a compound including at least three epoxy functional groups. | 01-16-2014 |
20160028410 | DELAY CELL, DELAY LOCKED LOOK CIRCUIT, AND PHASE LOCKED LOOP CIRCUIT - A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell. | 01-28-2016 |
Dong-Hyuk Park, Seoul KR
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20100075145 | METAL-POLYMER HYBRID NANOMATERIALS, METHOD FOR PREPARING THE SAME METHOD FOR CONTROLLING OPTICAL PROPERTY OF THE SAME OPTOELECTRONIC DEVICE USING THE SAME - Metal-polymer hybrid nanomaterials are provided. The hybrid nanomaterials comprise nanotubes or nanowires and metal layers formed on the inner or outer surfaces of the nanotubes or the outer surfaces of the nanowires. The nanotubes or nanowires include a light-emitting π-conjugated polymer and the metal layers are composed of a metal whose surface plasmon energy level is close to the energy band gap of the nanotubes or nanowires. Further provided are a method for preparing the hybrid nanomaterials, a method for controlling the optical properties of the hybrid nanomaterials, and an optoelectronic device using the hybrid nanomaterials. Energy transfer and electron transfer based on surface plasmon resonance increases the number of excitons in the conduction band of the nanotubes or nanowires including the light- emitting polymer, resulting in a remarkable increase in the luminescence intensity of the metal-polymer hybrid nanomaterials. The metal-polymer hybrid nanomaterials are easy to prepare and inexpensive while possessing inherent electrical and optical properties of carbon nanotubes. In addition, the electrical and optical properties of the metal-polymer hybrid nanomaterials can be easily controlled. Based on these advantages, the metal-polymer hybrid nanomaterials can be applied to a variety of optoelectronic devices, including light-emitting diodes, solar cells and photosensors. | 03-25-2010 |
20110282021 | Apparatus and Method for Modifying Physical Properties of Nanostructure Using Focused Electron Beam, and Nano-Barcode and Serial-Junction Nanowire Fabricated Thereby - According to one embodiment of the present invention, a portion of a light-emitting polymer material or a conductive polymer material can be irradiated with a focused electron beam, so that the physical properties of that portion can be modified. For this purpose, one embodiment of the present invention comprises an apparatus for modifying the physical properties of a nanostructure using a focused electron beam, the apparatus comprising: a nanostructure; a focused electron beam-irradiating unit that serves to irradiate a nanoscale electron beam such that it is focused on the nanostructure; and a focused electron beam-controlling unit that serves to control the irradiation position of the nanoscale electron beam so as to modify the physical property of a portion of the nanostructure. | 11-17-2011 |
20120257092 | PIXEL, PIXEL ARRAY, IMAGE SENSOR INCLUDING THE SAME AND METHOD FOR OPERATING THE IMAGE SENSOR - Disclosed are a pixel, a pixel array, an image sensor including the pixel array and a method for operating the image sensor. The pixel includes a photo-electro conversion unit; a capacitor for storing charges converted by the photo-electro conversion unit; an output switching device for outputting an electric potential of the capacitor; and a removal unit for removing a part of the charges converted by the photo-electro conversion unit. | 10-11-2012 |
20120257093 | PIXEL, PIXEL ARRAY, IMAGE SENSOR INCLUDING THE SAME AND METHOD FOR OPERATING THE IMAGE SENSOR - Disclosed are a pixel, a pixel array, an image sensor including the pixel array and a method for operating the image sensor. The pixel includes a photo-electro conversion unit; a first capacitor for storing a first quantity of charges of the photo-electro conversion unit; a second capacitor for storing a second quantity of charges of the photo-electro conversion unit; and an output unit to output the first and second quantities of the charges. | 10-11-2012 |
20120278019 | APPARATUS AND METHOD FOR COMPUTING COUPLING NOISE VOLTAGE OCCURRING IN FLASH MEMORY DEVICE - An apparatus for computing a coupling noise voltage occurring in a plurality of cells arranged on a plurality of word lines and a plurality of bit lines in a flash memory device includes: a coupling ratio computing unit and a coupling voltage computing unit. The coupling ratio computing unit can compute coupling ratios between a cell and neighboring cells wherein each of the coupling ratios have a value such that the difference between two coupling noise voltage values is minimized. The coupling voltage computing unit computes the coupling noise voltage value occurring in the cell using the computed coupling ratios. | 11-01-2012 |
Dong-Hyuk Yang, Seoul KR
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20110053635 | APPARATUS TO MODIFY APPLICATIONS OF MOBILE TERMINAL - An experience modification apparatus for a mobile terminal generates a modification event upon detecting execution of an application provided by the mobile terminal or upon detecting a specific order of key inputs so as to modify the applications of the mobile terminal. | 03-03-2011 |